Abstract: A modular multi-level power converter device including an AC output, including a modular multi-level DC/AC converter including a plurality of arms in parallel, ends of which define input terminals, each arm including two lines of modules in series, each switching module including a pair of switches in series, mounted on terminals of an energy-storage device, the DC/AC converter adjusting frequency at an output of the converter device. The device further includes a converter including a DC output, including two output terminals connected to the input terminals of the DC/AC converter, the converter including a DC output adjusting amplitude at an output of the converter device, the DC/AC converter further including a mechanism controlling the switches of the modules, which apply a full-wave command to the switches during at least one time interval, the modules of a single line being in a same state simultaneously.

Abstract: A modular multi-level power converter device including an AC output, including a modular multi-level DC/AC converter including a plurality of arms in parallel, ends of which define input terminals, each arm including two lines of modules in series, each switching module including a pair of switches in series, mounted on terminals of an energy-storage device, the DC/AC converter adjusting frequency at an output of the converter device. The device further includes a converter including a DC output, including two output terminals connected to the input terminals of the DC/AC converter, the converter including a DC output adjusting amplitude at an output of the converter device, the DC/AC converter further including a mechanism controlling the switches of the modules, which apply a full-wave command to the switches during at least one time interval, the modules of a single line being in a same state simultaneously.

Abstract: A multi-level power converter comprising: n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral Point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter); an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted

Abstract: This is a multi-level converter comprising at least one arm (B) formed of n stages (Et1, Et2, . . . , Etn) mounted in cascade. The first stage (Et1) comprises a single switching structure (Ce10) with four voltage levels and an ith stage (i lying between two and n) comprises i identical switching structures (Cei1, Cei2, . . . Ceii) with four voltage levels, mounted in series. Each switching structure with four voltage levels comprises a cell of floating capacitor type (T1, T2, T1?, T2?, C12), two basic switching cells (T3u, T3?u; T3l, T3?l) and a capacitive divider bridge (C9, C10, C11), the basic switching cells being connected between the voltage divider bridge and the cell of floating capacitor type.

Abstract: This is a multi-level converter comprising one or more arms (B) to each be connected between a voltage source (VDC) and a current source (I). Each arm comprises two stages (E1, E2) in cascade, the first to be connected to the voltage source (VDC), the second to be connected to the current source (I). The first stage (Et1) comprises several elementary stages (E1n, . . . , E12, E11) of rank one to n in cascade, the elementary stage (E11) of rank one being connected to the second stage (Et2) and the elementary stage (E1n) of rank n having to be connected to the voltage source (VDC). Each elementary stage (E1n) comprises a pair of identical cells of NPC type (Cen1, Cen2) in series, the connection being direct in the elementary stage of rank 1, the connection being made via n?1 capacitive cells ((Can(1), . . . , Can(n?1)) for each elementary stage of rank greater than one, the second stage (Et2) comprising a floating capacitor cell (Ce10).

Abstract: This is a multi-level converter comprising at least one arm (B) formed of n stages (Et1, Et2, . . . , Etn) mounted in cascade. The first stage (Et1) comprises a single switching structure (Ce10) with four voltage levels and an ith stage (i lying between two and n) comprises i identical switching structures (Cei1, Cei2, . . . Ceii) with four voltage levels, mounted in series. Each switching structure with four voltage levels comprises a cell of floating capacitor type (T1, T2, T1?, T2?, C12), two basic switching cells (T3u, T3?u; T3l, T3?l) and a capacitive divider bridge (C9, C10, C11), the basic switching cells being connected between the voltage divider bridge and the cell of floating capacitor type.

Abstract: The invention relates to a multi-level power converter comprising:—n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter),—an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), N

Abstract: This is a multi-level converter comprising one or more arms (B) to each be connected between a voltage source (VDC) and a current source (I). Each arm comprises two stages (E1, E2) in cascade, the first to be connected to the voltage source (VDC), the second to be connected to the current source (I). The first stage (Et1) comprises several elementary stages (E1n, . . . , E12, E11) of rank one to n in cascade, the elementary stage (E11) of rank one being connected to the second stage (Et2) and the elementary stage (E1n) of rank n having to be connected to the voltage source (VDC). Each elementary stage (E1n) comprises a pair of identical cells of NPC type (Cen1, Cen2) in series, the connection being direct in the elementary stage of rank 1, the connection being made via n?1 capacitive cells ((Can(1), . . . Can(n?1)) for each elementary stage of rank greater than one, the second stage (Et2) comprising a floating capacitor cell (Ce10).

Abstract: An on-load transformer tap changing system, for example for a power transformer, wherein the secondary or primary of a transformer includes at least one first tap and one second tap. A main connection circuit is used for permanent connection of the first tap or the second tap to an output terminal of the secondary or primary of the transformer. Secondary connection circuits are each used to connect a tap temporarily and directly to the output terminal of the secondary or primary of the transformer. Each of the connection circuits includes one or more insulated gate bipolar transistors. The system can be controlled without zero current value transition detection in the secondary winding.

Abstract: The invention relates to an on-load transformer tap changing system wherein the secondary or primary of a transformer comprises at least one first and one second taps (p1, p2). A main connection circuit (tra-I2) is used for the permanent connection of the first tap (p1) or the second tap (p2) to an output terminal (b2) of the secondary or primary of the transformer. Secondary connection circuits (I1, I3) are each used to connect a tap (p1, p2) temporarily and directly to said output terminal (b2) of the secondary or primary of the transformer. Each of said connection circuits (I1, tra-I2, I3) comprises one or more insulated gate bipolar transistors and the system can be controlled without zero current value transition detection in the secondary winding. Application: Power transformers.

Abstract: A multilevel converter including, in particular, a capacitor for each of its cells, and control means comprising means for evaluating the mean voltage across the terminals of each of the capacitors, means for measuring any difference on each of said capacitors between the evaluated mean charge voltage and the nominal mean charge voltage of the capacitor, and additional control means changing the time positions of the converter control signals in a direction such that the measured difference is reduced.

Abstract: A multilevel converter comprising, in particular, a capacitor (C1, C2, . . . , Cn) in each of its cells. The capacitors nominally have charge voltages proportional to their respective ranks in the converter. The converter also includes circuits (VMO1, VMO2, . . . , VMOn) for evaluating the mean voltage across the terminals of each of the capacitors (C1, C2, . . . , Cn), circuits (VE1, VE2, . . . , VEn) for measuring any difference that may occur with respect to each of the capacitors (C1, C2, . . . , Cn) between the evaluated mean charge voltage and the nominal mean charge voltage of the capacitor, and for providing a corresponding difference signal (VEC1, VEC2, . . . , VECn), and also correction control circuits (BT, EC1, EC2, . . . , ECn) receiving the difference signals and correspondingly causing at least one temporary coupling to be established between two capacitors in order to correct the difference.

Abstract: The control path of the switch (I) comprises an input stage (T2, T1) having an input (H) coupled to the input (E) for the control signal and having its output coupled to the control electrode (G) of the switch (I). A protection circuit (D1, Z2) coupled between the load (C) and the control path includes a threshold effect component (Z2) and a decoupling element (D1). On being made conductive by the current that results from a surge generated in a circuit of the load (C), the protection circuit (D1, Z2) is coupled to the input (H) of said input stage (T2, T1) to act on said switch (I) in the same way as a control signal for the switch (I). In this manner, the control path prevents current in the load (C) from dropping off suddenly.

Abstract: A multilevel converter comprising, in particular, one capacitor (C1, C2, . . . , Cn) and two switches (T1, T'1; for example) in each of its cells. The cells operate successively in a period that repeats at a converter frequency. In parallel with the load (C), a filter circuit (CF) is provided to dissipate the energy of any component having a fundamental frequency that corresponds to said converter period. The filter comprises one or more RLC type series circuits.

Abstract: A multilevel converter including, in particular, a capacitor (C1, C2, . . . , Cn) for each of its cells, and control means comprising means (VMO1, VMO2, . . . , VMOn) for evaluating the mean voltage across the terminals of each of the capacitors (C1, C2, . . . , Cn), means (VE1, VE2, . . . , VEn) for measuring any difference on each of said capacitors (C1, C2, . . . , Cn) between the evaluated mean charge voltage and the nominal mean charge voltage of the capacitor, and additional control means (MCC1, MCC2, . . . , MCCn) changing the duration of said first conduction state of the cell associated with said capacitor in a direction such that the measured difference is reduced.

Abstract: A multilevel converter including, in particular, a capacitor (C1, C2, . . . , Cn) for each of its cells. The capacitors have nominal charge voltages proportional to their respective ranks in the converter. It also includes control means (BT, DA1, . . . , DAn, pe2, . . . , pen) organized to evaluate said voltage of the voltage source (VECn), and whenever it is insufficient, to suspend said nominal operation of the converter (SE) and to act on said switches (T1, T'1; T2; T'2; . . . ; Tn, T'n) in such a manner that initially, while said voltage of the voltage source is being established, it begins by charging all of the capacitors of the converter (C1, C2, . . . , Cn), after which said control means establish said nominal operation of the converter.