Abstract: A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST structure with a redundancy mechanism. The circuit allows a two-pass fuse blow after completing the burn-in process that significantly increases the manufacturing yield and repairability of the SRAM macro.

Abstract: An integrated circuit incorporating at least a SRAM that includes memory, a data-out shift register, an ABIST data compression circuit, a fail address register and an array clock generator (ACG), the ACG comprising a clock chopper that comprises a first AND gate having an inherent delay DEL1, a first input for receiving a D clock signal, a second input for receiving the D signal inverted by an invertor having an inherent delay DEL2, and an output that generates an ungated LSSSD C clock signal; and a second AND gate having an inherent delay DEL4, a first input connected to the output of an inverter having an inherent delay DEL3, the inverter is coupled to the invertor having the delay DEL2, a second input is controlled by the D clock signal and an output for generating LSSD clock signals B and S.