Abstract: The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film.

Abstract: The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film.

Abstract: This invention describes a software method for computers for solving integer programming problems containing systems of linear equations where part of or all of the variables may take only integer values. Said software method consists of 4 main steps. First, all of or part of said system is transformed into a regularized system. In a second step, the regularized system is further transformed into an ordered system. In a third step, the regularized and ordered system is further transformed into a non-interfering system. In a last step, solutions to said system are determined by finding solutions which are common to all equations of said system. This is done by using a successive and recursive approximation algorithm. Finally, prior to executing said 4 steps, said system may have to be conditioned such every variable-coefficient of the system is non-zero.

Abstract: This invention describes a software method for computers for solving integer programming problems containing systems of linear equations where part of or all of the variables may take only integer values. Said software method consists of 2 main steps. First, the arithmetic binary decision diagrams associated to the equations of the system are constructed. A solution to any of said equations is determined by finding an allowed path through the associated arithmetic binary decision diagram. Then, solutions common to all equation of the system are determined by searching for common paths between the arithmetic binary decision diagrams of the equations. Searching for common paths between said arithmetic binary decision diagrams is done by determining correspondences between the nodes of said arithmetic binary decision diagrams.

Abstract: This invention describes a software method for computers for solving integer programming problems containing systems of linear equations where part of or all of the variables may take only integer values. Said software method consists of 3 main steps. First, all of or part of said system is regularized such that the variable-coefficients of the regularized part of said system satisfy some well defined properties. In a second step, parameterized solutions are computed for each equation of said system. In a third step, solutions to said system are determined by finding solutions which are common to all equations of said system. Furthermore, the solutions of an equation of said system may be determined by sorting two or more of the variable-coefficients of a said equation according to ascending or descending magnitude. Finally, prior to executing said 3 steps, said system may be conditioned such any variable-coefficient of the system is non-zero.

Abstract: The invention describes a method for executing structured symbolic machine code on a microprocessor. Said structured symbolic machine code contains a set of one or more regions, where each of said regions contains symbolic machine code containing, in addition to the proper instructions, information about the symbolic variables, the symbolic constants, the branch tree, pointers and functions arguments used within each of said regions. This information is fetched by the microprocessor from the instruction cache and stored into dedicated memories before the proper instructions of each region are fetched and executed. Said information is used by the microprocessor in order to improve the degree of parallelism achieved during instruction scheduling and execution. Among other purposes, said information allows the microprocessor to perform so-called speculative branch prediction.

Abstract: The invention describes a method for realizing autonomous load/store by using symbolic machine code. Instructions in symbolic machine code may have operands and/or results specifying symbolic variables. Symbolic variables naturally arise as the machine code pendant of pointer variables declared in a program written in some high level programming language. Formally, a symbolic variable specifies an entry in a dedicated memory other than a register file of said microprocessor. Said entry is used by the microprocessor in order to determine the definition address of said variable. By analyzing the symbolic variables specified as instruction operands and results and by writing the definition addresses of said symbolic variables into a heap address cache, the microprocessor dynamically determines the lifetimes of the values of said variables and, based on the lifetimes, determines where in the memory hierarchy said values will be stored.

Abstract: The present invention introduces a configurable register file architecture of a processing device (microprocessor, CPU, DSP) with multi-range shift register support. Said register file has two working modes which can be simultaneously active such that in addition to behaving as a conventional register file, said register file can also be configured such that the registers of said register file form one or more shift registers whose ranges are specified by dedicated ‘range control’ inputs of said register file. By incorporating the functionality of shift registers into the register file, register renaming is achieved at almost no hardware overhead, allowing furthermore a reduction in overall power consumption and machine code size.

Abstract: The present invention describes a microprocessor (CPU, DSP, micro-controller, ASIP etc. ) having an instruction format containing timing information. Said timing information is contained in one or more bit-fields of said instruction format and determines instruction scheduling and execution when a machine code running on said microprocessor. Said instruction format refers as well to ‘implicit’ instructions and to ‘implicit and potential’ instructions where the instruction is not explicitly specified by an ‘opcode’ bit-field in the instruction format.

Abstract: An integrated circuit has a matrix of programmable cells. Programmable switches connect pairs of neighboring cells. Each cell contains a local conductor connecting a pair of the switches on opposite sides of the cell. Each switch connects the local conductors of the neighboring cells. At least one of the cells have a computation logic circuit having either an input connected to the local conductor of the at least one of the cells. The computation logic circuit has programmably individually activatable outputs connected to the local conductors of neighbor cells of the at least one of the cells or an output connected to the local conductor of the at least one of the cells and programmably individually activatable inputs connected to the local conductors of neighbor cells of the at least one of the cells.