Abstract: A solid-state microbattery, including a substrate; a lithium-cobalt-oxide layer forming a cathode having first and second opposite surfaces; a lithium-based solid-state electrolyte formed on the first surface of the cathode; the second surface of the cathode is oriented towards the substrate; an anode formed on the solid-state electrolyte; noteworthy in that the lithium-cobalt-oxide layer possesses a grain size that increases from the first surface to the second surface.

Abstract: A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.

Abstract: The present description concerns a method of manufacturing a vapor chamber (300) comprising the following steps: (a) etching, in a first substrate (301), at least one first cavity (303) and at least one channel (313) extending from an upper surface (305) of said first substrate (301), a first end (315) of said channel (313) emerging into said at least one cavity (303); (b) bonding a lower surface of a plate (309) to the upper surface (305) of said first substrate (301), the plate (309) comprising at least one first region made of a ductile material (321) arranged in front of said first end (315) of said channel (313); (c) filling said channel (313) with a cooling fluid (319); and (d) closing said cavity (303) by applying a pressure on said region of ductile material of the plate (309) to obstruct said first end (315) of said channel (313).

Abstract: A battery includes, stacked successively above a first face of a support, in a stacking direction, at least a cathode including a lower face, an upper face and a side wall directed in the stacking direction from the lower face to the upper face, a solid electrolyte, an anode, the battery including a coating portion surrounding, and in contact with, all of the side wall of the cathode, without covering the upper face of the cathode.

Abstract: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Abstract: A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.

Abstract: A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.

Abstract: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Abstract: The present invention relates to a method for manufacturing a cooling circuit on at least one integrated circuit chip (1), comprising producing a cooling circuit on a first face of the chip (1), characterised in that the production of the cooling circuit comprises: forming a definition pattern of the cooling circuit (4) on the first face of the chip (1), said pattern comprising at least one layer of a sacrificial material (42); coating (6) said pattern by at least one resin layer; at least partially removing the sacrificial material from said pattern so as to open the cooling circuit (2).

Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Abstract: A method for making a conducting structure comprising steps of: forming on a given face of the support comprising at least one conducting element, at least one area for absorbing stresses based on a dielectric material, forming at least one aperture in said dielectric material by applying a mold on said dielectric material, said aperture being provided with inclined walls relatively to a normal to the main plane of said support, the bottom of said aperture revealing said conducting element, filling said aperture with a conducting material.