Patents by Inventor Jean-Pierre Raskin

Jean-Pierre Raskin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923239
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20230411309
    Abstract: A structure for an RF device provided with a semiconductor region coated with a heterogeneous dielectric region, the heterogeneous dielectric region including, in at least one first direction parallel to a main plane of the substrate, an alternation of first areas made of a first dielectric material with positive fixed charges and of second dielectric areas made of a second dielectric material with negative fixed charge in order to create an alternation of polarity allowing preventing the formation of a parasitic conduction layer in the semiconductor region.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 21, 2023
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Louis HUTIN, Maxime MOULIN, Thibaud FACHE, Christophe PLANTIER, Jean-Pierre RASKIN, Martin RACK
  • Patent number: 11538689
    Abstract: A substrate has a front side including an electrical circuit and a rear side including an exposed zone that faces the electrical circuit. In an electrochemical treatment step, an electrical potential is laterally applied at least to the exposed zone of the rear side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes a lateral flow of electrical current at least in the exposed zone of the substrate. The lateral flow of current and the chemically reactive substance alter the substrate in at least the exposed zone.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 27, 2022
    Assignee: UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Gilles Scheen, Jean-Pierre Raskin, Jonathan Rasson
  • Publication number: 20220277988
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 11367650
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 21, 2022
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 11222944
    Abstract: An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 ?·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 11, 2022
    Assignee: UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Jean-Pierre Raskin, Martin Rack
  • Publication number: 20210143053
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Application
    Filed: December 2, 2020
    Publication date: May 13, 2021
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20210118977
    Abstract: An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 ?·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.
    Type: Application
    Filed: May 2, 2019
    Publication date: April 22, 2021
    Applicant: UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Jean-Pierre RASKIN, Martin RACK
  • Patent number: 10943815
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 9, 2021
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20200411324
    Abstract: A substrate has a front side including an electrical circuit and a rear side including an exposed zone that faces the electrical circuit. In an electrochemical treatment step, an electrical potential is laterally applied at least to the exposed zone of the rear side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes a lateral flow of electrical current at least in the exposed zone of the substrate. The lateral flow of current and the chemically reactive substance alter the substrate in at least the exposed zone.
    Type: Application
    Filed: March 22, 2019
    Publication date: December 31, 2020
    Inventors: Gilles SCHEEN, Jean-Pierre RASKIN, Jonathan RASSON
  • Patent number: 10819282
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Publication number: 20200169222
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Application
    Filed: May 23, 2018
    Publication date: May 28, 2020
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Patent number: 10429436
    Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 1, 2019
    Assignee: Soitec
    Inventors: Cédric Malaquin, Jean-Pierre Raskin, Eric Desbonnets
  • Publication number: 20190157137
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms·cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms·cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Application
    Filed: June 6, 2017
    Publication date: May 23, 2019
    Applicant: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20180024186
    Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.
    Type: Application
    Filed: January 19, 2016
    Publication date: January 25, 2018
    Applicant: Soitec
    Inventors: Cédric Malaquin, Jean-Pierre Raskin, Eric Desbonnets
  • Publication number: 20100224006
    Abstract: This invention provides an internal stress actuated micro- or nano-machine for measuring mechanical and/or electrical properties, e.g. traction measurement, compression measurement or shear measurement, on micro-scale and nano-scale films or multi-layers of materials such as metallic materials, carbon-based materials and silicon-base materials. The device of the invention has applications in materials production industry, as well as in micro-electronics and for surface treatments and functionalization.
    Type: Application
    Filed: February 14, 2007
    Publication date: September 9, 2010
    Inventors: Thomas Pardoen, Damien Fabrégue, Jean-Pierre Raskin, Nicolas André, Michaël Coulombier
  • Publication number: 20100057381
    Abstract: This invention provides a method and device for imposing and determining mechanical stress and/or strain, on micro-scale and nano-scale beams, films or multi-layers of materials such as metallic materials, polymer materials, ceramic materials, carbon-based materials and silicon-based materials using a set of micro- or nano-machines. The present invention also provides methods to derive and modify various properties or state of such nano- or microstructures, among others mechanical properties, and to measure the external stimulus that they are subjected to.
    Type: Application
    Filed: February 14, 2008
    Publication date: March 4, 2010
    Inventors: Thomas Pardoen, Jean-Pierre Raskin, Pierre Carbonnelle, Sébastien Gravier
  • Patent number: 7585748
    Abstract: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the electrical charge within the electrically insulating layer in order to minimize electrical losses in the structure support layer.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: September 8, 2009
    Assignees: S.O.I.Tec Silicon on Insulator Technologies, Université Catholique de Louvain
    Inventors: Jean-Pierre Raskin, Dimitri Lederer, François Brunier
  • Publication number: 20060166451
    Abstract: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the electrical charge within the electrically insulating layer in order to minimize electrical losses in the structure support layer.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 27, 2006
    Inventors: Jean-Pierre Raskin, Dimitri Lederer, Francois Brunier
  • Publication number: 20040152272
    Abstract: The present invention relates to a method for fabrication of semiconductor devices, in particular but not limited to the fabrication of double gate transistors of the type Gate-All-Around or “semiconductor-on-nothing” transistors and devices. A method according to the present invention comprises the steps of: (a) forming a trench in a least a first substrate, (b) transferring semiconductor material over the trench to form a semiconductor bridge across the trench, the semiconductor bridge defining an active area. The bridge may be free to oscillate above the trench without using removing a sacrificial layer. The method may also include the steps of: (c) forming a gate insulator on the semiconductor bridge, and (d) applying gate material on the gate insulator, thus forming a gate.
    Type: Application
    Filed: March 1, 2004
    Publication date: August 5, 2004
    Inventors: Denis Fladre, Amaury Neve De Mevergnies, Jean-Pierre Raskins