Abstract: The present disclosure relates to a nonwoven insect barrier net. The nonwoven insect barrier may be formed into a net structure for use over and/or surrounding a sleeping surface. The nonwoven insect barrier net may inhibit insects from penetrating the area within the net structure. The insect barrier may be formed from a nonwoven material and an insect repellant composition.

Abstract: A system for optimally mapping circuits into packets based on round trip delay (RTD), and a system for measuring RTD for use in packet communications systems such as circuit emulation (CEM) systems is disclosed. The measured RTD value can be used in a system that adjusts packet size to reduce capture delay to partially offset an increase in RTD. As the use of smaller packets increases the overhead burden on the packet communication system, the packet size can be increased to reduce the overhead burden when the size of the current RTD becomes appropriately short. The disclosure also teaches the placement of data from two or more circuits destined for the same emulation endpoint into the same transmission packet in order to improve system performance. The abstract is a tool for finding relevant disclosures and not a limitation on the scope of the claims.

Abstract: A system for optimally mapping circuits into packets based on round trip delay (RTD), and a system for measuring RTD for use in packet communications systems such as circuit emulation (CEM) systems is disclosed. The measured RTD value can be used in a system that adjusts packet size to reduce capture delay to partially offset an increase in RTD. As the use of smaller packets increases the overhead burden on the packet communication system, the packet size can be increased to reduce the overhead burden when the size of the current RTD becomes appropriately short. The disclosure also teaches the placement of data from two or more circuits destined for the same emulation endpoint into the same transmission packet in order to improve system performance. The abstract is a tool for finding relevant disclosures and not a limitation on the scope of the claims.

Abstract: A Phase-locked Loop (PLL) (204) that is dynamically and automatically altered in response to changes in the jitter of the input is disclosed. The Analysis Block (304) receives one or more inputs from the PLL operation. The output of the Analysis Block (304) triggers a change in the Parametric Control Block (308) which in turn imparts changes on the gains of one or more of the various components or the value of &ohgr;N of the PLL Low Pass Filter (116). The dynamic change to at least one parameter of the PLL adjusts the tradeoff between removing as much of the jitter as possible and having a responsive system that has a reduced risk of buffer underflow or overflow. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.