Patents by Inventor Jeanne Luce
Jeanne Luce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153947Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
-
Patent number: 11961838Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: GrantFiled: May 3, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
-
Publication number: 20220262795Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
-
Patent number: 11380683Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: GrantFiled: October 21, 2020Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
-
Publication number: 20210035972Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
-
Patent number: 10861850Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: GrantFiled: June 19, 2020Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
-
Publication number: 20200321333Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
-
Patent number: 10734379Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: GrantFiled: December 30, 2017Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
-
Patent number: 10693006Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: GrantFiled: July 19, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Publication number: 20190164961Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.Type: ApplicationFiled: December 30, 2017Publication date: May 30, 2019Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
-
Publication number: 20190013406Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: ApplicationFiled: July 19, 2018Publication date: January 10, 2019Applicant: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Patent number: 10056488Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: GrantFiled: January 6, 2017Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Publication number: 20170125596Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: ApplicationFiled: January 6, 2017Publication date: May 4, 2017Applicant: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Patent number: 9634124Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: GrantFiled: July 17, 2015Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Publication number: 20160020304Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: ApplicationFiled: July 17, 2015Publication date: January 21, 2016Applicant: INTEL CORPORATONInventors: Sameer Pradhan, Jeanne Luce
-
Patent number: 9087915Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: GrantFiled: December 6, 2011Date of Patent: July 21, 2015Assignee: Intel CorporationInventors: Sameer Pradhan, Jeanne Luce
-
Publication number: 20140117425Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: ApplicationFiled: December 6, 2011Publication date: May 1, 2014Inventors: Sameer Pradhan, Jeanne Luce