Patents by Inventor Jee Chang LAI

Jee Chang LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11646137
    Abstract: A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 9, 2023
    Assignee: X-FAB GLOBAL SERVICES GMBH
    Inventors: Guido Janssen, Klaus Heinrich, Tillmann Walther, Xuezhou Cao, Jee Chang Lai
  • Patent number: 11335791
    Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 17, 2022
    Assignee: X-FAB SARAWAK SDN. BHD.
    Inventors: Jerry Liew, Jee Chang Lai
  • Publication number: 20210249163
    Abstract: A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 12, 2021
    Inventors: Guido JANSSEN, Klaus HEINRICH, Tillmann WALTHER, Xuezhou CAO, Jee Chang LAI
  • Patent number: 10892182
    Abstract: A method of fabricating a semiconductor device with Shallow Trench Isolation (STI) includes performing the following steps in the following sequence: providing a substrate comprising first and second gate regions separated by a trench formed in the substrate, wherein the trench is filled with an STI material. The method further includes depositing a sacrificial polysilicon layer covering the STI material; growing a thick oxide layer on the first and second gate regions; removing the thick oxide layer from the first gate region while leaving the thick oxide layer in the second gate region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 12, 2021
    Assignee: X-FAB SARAWAK SDN. BHD.
    Inventors: Foo Sen Liew, Jee Chang Lai
  • Publication number: 20190355614
    Abstract: A method of fabricating a semiconductor device with Shallow Trench Isolation (STI) includes performing the following steps in the following sequence: providing a substrate comprising first and second gate regions separated by a trench formed in the substrate, wherein the trench is filled with an STI material. The method further includes depositing a sacrificial polysilicon layer covering the STI material; growing a thick oxide layer on the first and second gate regions; removing the thick oxide layer from the first gate region while leaving the thick oxide layer in the second gate region.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 21, 2019
    Applicant: X-FAB Sarawak Sdn. Bhd.
    Inventors: Foo Sen LIEW, Jee Chang LAI
  • Publication number: 20190355837
    Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 21, 2019
    Applicant: X-FAB Sarawak Sdn. Bhd.
    Inventors: Jerry LIEW, Jee Chang LAI