Abstract: A cover panel and a display device, the cover panel including a heat sink layer; an impact absorbing layer on the heat sink layer; and an elastic pattern on at least one side of the impact absorbing layer.

Abstract: A touch panel includes a plurality of sensing electrodes, a plurality of wirings and an electrostatic discharge pattern. The plurality of sensing electrodes is disposed on a substrate. The plurality of wirings extends from the plurality of sensing electrodes. A bottom surface of the plurality of wirings has the same height as a bottom surface of the plurality of sensing electrodes. The electrostatic discharge pattern is electrically connected to the plurality of wirings.

Abstract: A cover panel and a display device, the cover panel including a heat sink layer; an impact absorbing layer on the heat sink layer; and an elastic pattern on at least one side of the impact absorbing layer.

Abstract: A touch screen panel includes a touch substrate, first sensing electrodes, second sensing electrodes, and outer lines. The touch substrate includes a touch active area and a touch non-active area. The first and second sensing electrodes are disposed in the touch active area and insulated from each other while crossing each other. Each first sensing electrode includes a first sensing metal layer and a first transparent sensing electrode layer. Each second sensing electrode includes a second sensing metal layer and a second transparent sensing electrode layer. Each outer line includes a first outer metal layer, a transparent outer electrode layer, and a second outer metal layer.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.

Abstract: A touch panel includes a plurality of sensing electrodes, a plurality of wirings and an electrostatic discharge pattern. The plurality of sensing electrodes is disposed on a substrate. The plurality of wirings extends from the plurality of sensing electrodes. A bottom surface of the plurality of wirings has the same height as a bottom surface of the plurality of sensing electrodes. The electrostatic discharge pattern is electrically connected to the plurality of wirings.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.

Abstract: A conductive pattern forming method includes forming a conductive layer on a substrate. An organic pattern including a plurality of fillers condensed in a network shape is formed on the conductive layer. A conductive pattern to which the shapes of the plurality of fillers condensed in the network shape are transferred is formed by dry-etching the conductive layer using the organic pattern as a mask. The organic pattern is eliminated.

Abstract: A touch screen panel includes a touch substrate, first sensing electrodes, second sensing electrodes, and outer lines. The touch substrate includes a touch active area and a touch non-active area. The first and second sensing electrodes are disposed in the touch active area and insulated from each other while crossing each other. Each first sensing electrode includes a first sensing metal layer and a first transparent sensing electrode layer. Each second sensing electrode includes a second sensing metal layer and a second transparent sensing electrode layer. Each outer line includes a first outer metal layer, a transparent outer electrode layer, and a second outer metal layer.

Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.