Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cost-efficient high power PECVD deposition apparatus for solar cells
    Patent number: 10403779
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
    Publication number: 20190267475
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana
  • Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal
    Patent number: 10396229
    Abstract: A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joel P. De Souza, Harold J. Hovel, Daniel A. Inns, Jeehwan Kim, Christian Lavoie, Devendra K. Sadana, Katherine L. Saenger, Davood Shahrjerdi, Zhen Zhang
  • Silicon germanium-on-insulator formation by thermal mixing
    Patent number: 10396182
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana
  • SYSTEMS AND METHODS OF DISLOCATION FILTERING FOR LAYER TRANSFER
    Publication number: 20190259608
    Abstract: A method of manufacturing a semiconductor device includes forming a first epitaxial layer on a first substrate. The first substrate includes a first semiconductor material having a first lattice constant and the first epitaxial layer includes a second semiconductor material having a second lattice constant different from the first lattice constant. The method also includes disposing a graphene layer on the first epitaxial layer and forming a second epitaxial layer comprising the second semiconductor material on the graphene layer. This method can increase the substrate reusability, increase the release rate of functional layers, and realize precise control of release thickness.
    Type: Application
    Filed: November 8, 2017
    Publication date: August 22, 2019
    Applicant: Massachusetts Institute of Technology
    Inventors: Jeehwan Kim, Kyusang Lee
  • CONE-SHAPED HOLES FOR HIGH EFFICIENCY THIN FILM SOLAR CELLS
    Publication number: 20190259886
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Selective epitaxy using epitaxy-prevention layers
    Patent number: 10388522
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Cone-shaped holes for high efficiency thin film solar cells
    Patent number: 10388808
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Optoelectronics integration by transfer process
    Patent number: 10374159
    Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Tze-bin Song
  • THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL
    Publication number: 20190237597
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Porous fin as compliant medium to form dislocation-free heteroepitaxial films
    Patent number: 10366881
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • STRAIN SENSOR UNIT AND SKIN SENSOR MODULE COMPRISING THE SAME
    Publication number: 20190223762
    Abstract: A strain sensor unit and a skin sensor module comprising the same are provided. The strain sensor unit according to an embodiment of the present disclosure includes a substrate having a through-hole, and including a first electrode and a second electrode formed at one side and the other side of the through-hole on one surface of the substrate, a piezoelectric device drawn from the first electrode and extending inward the through-hole, and a piezoresistor drawn from the second electrode and extending inward the through-hole, wherein the piezoresistor overlaps with a whole or part of the piezoelectric device.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Jiyeon HAN, Han-Wool YEON, Eunjoo KIM, Jeehwan KIM, Kyusang LEE, Haekwang LEE
  • Atomic layer deposition for photovoltaic devices
    Patent number: 10355160
    Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, David B. Mitzi, Byungha Shin, Teodor K. Todorov, Mark T. Winkler
  • COST-EFFICIENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS
    Publication number: 20190214519
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 11, 2019
    Inventors: TZE-CHIANG CHEN, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Three-dimensional conductive electrode for solar cell
    Patent number: 10347779
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Cost-efficient high power PECVD deposition for solar cells
    Patent number: 10319872
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Photovoltaic devices with an interfacial band-gap modifying structure and methods for forming the same
    Patent number: 10297709
    Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 21, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, EGYPT NANOTECHNOLOGY CENTER
    Inventors: Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, George S. Tulevski, Ahmed Abou-Kandil, Hisham S. Mohamed, Mohamed Saad, Osama Tobail
  • STRAIN SENSOR UNIT AND SKIN SENSOR MODULE COMPRISING THE SAME
    Publication number: 20190133491
    Abstract: A strain sensor unit and a skin sensor module comprising the same are provided. The strain sensor unit according to an embodiment of the present disclosure includes a substrate having a through-hole, and including a first electrode and a second electrode formed at one side and the other side of the through-hole on one surface of the substrate, a piezoelectric device drawn from the first electrode and extending inward the through-hole, and a piezoresistor drawn from the second electrode and extending inward the through-hole, wherein the piezoresistor overlaps with a whole or part of the piezoelectric device.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Jiyeon HAN, Han-Wool YEON, Eunjoo KIM, Jeehwan KIM, Kyusang LEE, Haekwang LEE
  • Photovoltaic devices with an interfacial band-gap modifying structure and methods for forming the same
    Patent number: 10283668
    Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 7, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, EGYPT NANOTECHNOLOGY CENTER
    Inventors: Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, George S. Tulevski, Ahmed Abou-Kandil, Hisham S. Mohamed, Mohamed Saad, Osama Tobail
  • POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
    Publication number: 20190109056
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 11, 2019
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana