Patents by Inventor Jeff A. McClain
Jeff A. McClain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11361808Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: October 15, 2018Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Patent number: 11264075Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: October 15, 2018Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Patent number: 10930335Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: December 21, 2018Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20190130961Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may he configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: December 21, 2018Publication date: May 2, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20190051344Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: DEBRA M. BELL, Jeff A. McClain, Brian P. Callaway
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Patent number: 10134461Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: May 8, 2015Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20150243339Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Inventors: DEBRA M. BELL, Jeff A. McClain, Brian P. Callaway
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Patent number: 9047978Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: August 26, 2013Date of Patent: June 2, 2015Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20150055420Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: August 26, 2013Publication date: February 26, 2015Applicant: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Patent number: 6584010Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: August 30, 2001Date of Patent: June 24, 2003Assignee: Micron Technology, Inc.Inventor: Jeff A. McClain
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Patent number: 6496408Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: August 30, 2001Date of Patent: December 17, 2002Assignee: Micron Technology, Inc.Inventor: Jeff A. McClain
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Patent number: 6493252Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: August 15, 2001Date of Patent: December 10, 2002Inventor: Jeff A. McClain
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Patent number: 6430082Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: August 30, 2001Date of Patent: August 6, 2002Assignee: Micron Technology, Inc.Inventor: Jeff A. McClain
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Patent number: 6430081Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: August 30, 2001Date of Patent: August 6, 2002Assignee: Micron Technology, Inc.Inventor: Jeff A. McClain
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Publication number: 20020024841Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: ApplicationFiled: August 30, 2001Publication date: February 28, 2002Applicant: Micron Technology, Inc.Inventor: Jeff A. McClain
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Publication number: 20020006055Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: ApplicationFiled: August 30, 2001Publication date: January 17, 2002Applicant: Micron Technology, Inc.Inventor: Jeff A. McClain
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Publication number: 20020006056Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: ApplicationFiled: August 30, 2001Publication date: January 17, 2002Applicant: Micron Technology, Inc.Inventor: Jeff A. McClain
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Publication number: 20020003718Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: ApplicationFiled: August 30, 2001Publication date: January 10, 2002Applicant: Micron Technology, Inc.Inventor: Jeff A. McClain
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Patent number: 6292387Abstract: Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.Type: GrantFiled: January 20, 2000Date of Patent: September 18, 2001Assignee: Micron Technology, Inc.Inventor: Jeff A. McClain