Abstract: Digitizing objects in a picture is discussed herein. A user presents the object to a camera, which captures the image comprising color and depth data for the front and back of the object. For both front and back images, the closest point to the camera is determined by analyzing the depth data. From the closest points, edges of the object are found by noting large differences in depth data. The depth data is also used to construct point cloud constructions of the front and back of the object. Various techniques are applied to extrapolate edges, remove seams, extend color intelligently, filter noise, apply skeletal structure to the object, and optimize the digitization further. Eventually, a digital representation is presented to the user and potentially used in different applications (e.g., games, Web, etc.).

Abstract: A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.

Abstract: A method and apparatus for reseting, for example, a Flash electrically erasable programmable read-only memory (EEPROM) having a microcontroller, the method and apparatus receiving a reset signal and, in response to said reset signal: determining if said microcontroller is performing an algorithm that manipulates a voltage and if said microcontroller is performing such an algorithm, performing a first operation to change the voltage, and performing a second operation to reset a logic.

Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Abstract: A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Abstract: An integrated circuit arrangement which provides a self regulated pump supply for a flash EEPROM memory cell pair reference circuit. The integrated circuit arrangement comprises: a charge pump circuit; a source of reference voltages; a comparator for comparing an output of the charge pump with a reference voltage and for operating the charge pump based on its output; and a pass device for coupling an output of the charge pump to the comparator.

Abstract: A method and apparatus for controlling a charge pump. A detection circuit is used to assert a detect signal when a power supply voltage exceeds a first threshold voltage and deassert the detect signal in response to a trigger. The detect signal is used to force a charge pump to operate in a mode that drives the capacitive node at its output to the target voltage with reduced latency. This is particularly useful for a device which may operate the charge pump in a reduced power mode which is designed to maintain the node voltage at reduced power rather than drive it to the degree necessary for reduced latency during power up.

Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.