Abstract: Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives an voltage existing across the second and third terminals of the transistor, generates an isolated voltage and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

Abstract: Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives an voltage existing across the second and third terminals of the transistor, generates an isolated voltage and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

Abstract: Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives a voltage existing across the second and third terminals of the transistor and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

Abstract: A hysteretic regulator is provided. The hysteretic regulator includes a delay compensation circuit that adds a delay to the output of the hysteretic comparator. The delay is dependent on the input voltage. For low duty cycles, the slope of the inductor current is much greater for the rising edge than it is for the falling edge. The delay compensation circuit adds sufficient delay to the falling edge so that the undershoot cancels the overshoot.

Abstract: A DC-to-DC converter having multiple power channels and a switching controller which generates a pulse-width modulated control signal for each power channel, and a switching controller for use in (and a method for generating power switch control signals for) such a converter. The control signals are generated in response to trigger signal trains generated by trigger channels. The trigger channels rotate relative to the power channels so that the control signals are generated in response to a sequence of trigger channel states. In some embodiments, the controller has one control signal channel and one trigger channel for each power channel. In other embodiments, there are N power channels, N control signal channels, and M reset channels (each for generating a trigger signal train), where M is an integer greater than N. The extra channel or channels is used for preventing rotation errors which would otherwise delay opening of the closed power switches.