Patents by Inventor Jeff Rysinski
Jeff Rysinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312842Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: GrantFiled: December 15, 2014Date of Patent: April 12, 2016Assignee: SK Hynix Inc.Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Patent number: 9312841Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: GrantFiled: December 15, 2014Date of Patent: April 12, 2016Assignee: SK Hynix Inc.Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Publication number: 20150102840Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: ApplicationFiled: December 15, 2014Publication date: April 16, 2015Inventors: Jeff RYSINSKI, Yibing Michelle WANG, Sang-Soo LEE
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Publication number: 20150097596Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Inventors: Jeff RYSINSKI, Yibing Michelle WANG, Sang-Soo LEE
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Patent number: 8988111Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: GrantFiled: January 31, 2011Date of Patent: March 24, 2015Assignee: SK Hynix Inc.Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Patent number: 8823850Abstract: An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.Type: GrantFiled: December 30, 2010Date of Patent: September 2, 2014Assignee: Hynix Semiconductor Inc.Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Patent number: 8749665Abstract: A system for processing images may comprise a pixel configuration circuitry enabled to set for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains. A column analog-to-digital converter may be enabled to generate a corresponding digital data for a pixel in the pixel array, and digital processing circuitry may be enabled to interpolate output data from the corresponding digital data for pixels grouped into pixel groups, wherein the pixel group comprises a target pixel and neighboring pixels in a same color plane.Type: GrantFiled: January 31, 2011Date of Patent: June 10, 2014Assignee: SK Hynix Inc.Inventors: Yibing Michelle Wang, Jeff Rysinski, Hongyu Wang
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Patent number: 8456557Abstract: Aspects of the invention provide dynamic range extension for CMOS image sensors for mobile applications. An embodiment of the invention may comprise setting for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains, wherein the settings may be used to generate corresponding digital data for each pixel in the pixel array. The corresponding digital data for adjacent pixels for the same color plane may then be grouped into a superpixel, where each pixel has associated with it a different combination of integration time and signal gain.Type: GrantFiled: January 31, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Yibing Michelle Wang, Jeff Rysinski, Hongyu Wang
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Patent number: 8390486Abstract: Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.Type: GrantFiled: May 31, 2011Date of Patent: March 5, 2013Assignee: SK Hynix Inc.Inventors: Yibing Michelle Wang, Jeff Rysinski, Hongyu Wang, Sang-Soo Lee
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Patent number: 8368570Abstract: Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.Type: GrantFiled: January 31, 2011Date of Patent: February 5, 2013Assignee: SK Hynix Inc.Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Publication number: 20120306674Abstract: Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yibing Michelle WANG, Jeff RYSINSKI, Hongyu WANG, Sang-Soo LEE
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Publication number: 20120194261Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jeff RYSINSKI, Yibing Michelle WANG, Sang-Soo LEE
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Publication number: 20120194252Abstract: Aspects of the invention provide, inter alia, techniques for shifting auto-zero voltage in analog comparators. An embodiment of the invention may include at least one diode configured transistor to increase a drain voltage of at least one NMOS load transistor. A first switch and a second switch may be implemented to increase a voltage at a gate of a first PMOS input transistor and a voltage at a gate of a second PMOS input transistor when the first switch and the second switch are closed.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jeff RYSINSKI, Sang-Soo LEE
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Publication number: 20120195502Abstract: A system for processing images may comprise a pixel configuration circuitry enabled to set for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains. A column analog-to-digital converter may be enabled to generate a corresponding digital data for a pixel in the pixel array, and digital processing circuitry may be enabled to interpolate output data from the corresponding digital data for pixels grouped into pixel groups, wherein the pixel group comprises a target pixel and neighboring pixels in a same color plane.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yibing Michelle WANG, Jeff RYSINSKI, Hongyu WANG
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Publication number: 20120194722Abstract: Aspects of the invention provide dynamic range extension for CMOS image sensors for mobile applications. An embodiment of the invention may comprise setting for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains, wherein the settings may be used to generate corresponding digital data for each pixel in the pixel array. The corresponding digital data for adjacent pixels for the same color plane may then be grouped into a superpixel, where each pixel has associated with it a different combination of integration time and signal gain.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yibing Michelle WANG, Jeff RYSINSKI, Hongyu WANG
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Publication number: 20120194368Abstract: Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jeff RYSINSKI, Yibing Michelle WANG, Sang-Soo LEE
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Publication number: 20120169909Abstract: An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Inventors: Jeff RYSINSKI, Yibing Michelle Wang, Sang-Soo Lee