Abstract: According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.

Abstract: In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.