Patents by Inventor Jeff Zhiqiang Wu
Jeff Zhiqiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6653220Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: August 3, 2001Date of Patent: November 25, 2003Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6404018Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1×1016 ions/cm3; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1×1019 ions/cm3 and the drain having a third average n-type dopant concentration of at least 1×1019 ions/cm3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.Type: GrantFiled: May 2, 2000Date of Patent: June 11, 2002Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Publication number: 20020004297Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: ApplicationFiled: August 3, 2001Publication date: January 10, 2002Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6309935Abstract: Methods of forming field effect transistors.Type: GrantFiled: June 3, 1998Date of Patent: October 30, 2001Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Sittampalam Yoganathan
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Patent number: 6281109Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: May 15, 2000Date of Patent: August 28, 2001Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6184539Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.Type: GrantFiled: May 4, 1998Date of Patent: February 6, 2001Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 6144068Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions.Type: GrantFiled: March 25, 1999Date of Patent: November 7, 2000Assignee: Micron Technology, Inc.Inventors: David Y. Kao, Jeff Zhiqiang Wu
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Patent number: 6140685Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.Type: GrantFiled: April 30, 1999Date of Patent: October 31, 2000Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 6066548Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: October 31, 1996Date of Patent: May 23, 2000Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6063673Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions.Type: GrantFiled: August 31, 1998Date of Patent: May 16, 2000Assignee: Micron Technology, Inc.Inventors: David Y. Kao, Jeff Zhiqiang Wu
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Patent number: 6022783Abstract: A semiconductor processing method of forming an NMOS field effect transistor includes, a) providing a projecting mesa of semiconductive material from a bulk semiconductor substrate, the mesa defining a semiconductor substrate floor and walls rising upwardly therefrom; b) providing a gate dielectric layer and a gate atop the semiconductive mesa; c) providing a pair of opposing LDD regions within the semiconductive mesa, the respective LDD regions running along one of the mesa walls; and d) providing source and drain diffusion regions within the bulk semiconductor substrate floor which respectively interconnect with the opposing LDD regions of the mesa. NMOS field effect transistors are also disclosed.Type: GrantFiled: July 30, 1997Date of Patent: February 8, 2000Assignee: Micron Technology, Inc.Inventor: Jeff Zhiqiang Wu
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Patent number: 5976926Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.Type: GrantFiled: October 10, 1997Date of Patent: November 2, 1999Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 5955760Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions.Type: GrantFiled: May 19, 1997Date of Patent: September 21, 1999Assignee: Micron Technology, Inc.Inventors: David Y. Kao, Jeff Zhiqiang Wu
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Patent number: 5897357Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impuritType: GrantFiled: September 20, 1996Date of Patent: April 27, 1999Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Sittampalam Yoganathan
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Patent number: 5811338Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the. substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions.Type: GrantFiled: August 9, 1996Date of Patent: September 22, 1998Assignee: Micron Technology, Inc.Inventors: David Y. Kao, Jeff Zhiqiang Wu
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Patent number: 5780906Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.Type: GrantFiled: February 10, 1997Date of Patent: July 14, 1998Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 5773358Abstract: Methods of forming field effect transistors.Type: GrantFiled: August 12, 1996Date of Patent: June 30, 1998Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Sittampalam Yoganathan
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Patent number: 5770497Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.Type: GrantFiled: January 27, 1997Date of Patent: June 23, 1998Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 5757051Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate -the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.Type: GrantFiled: November 12, 1996Date of Patent: May 26, 1998Assignee: Micron Technology, Inc.Inventors: Jeff Zhiqiang Wu, Joseph Karniewicz
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Patent number: 5721443Abstract: A semiconductor processing method of forming an NMOS field effect transistor includes, a) providing a projecting mesa of semiconductive material from a bulk semiconductor substrate, the mesa defining a semiconductor substrate floor and walls rising upwardly therefrom; b) providing a gate dielectric layer and a gate atop the semiconductive mesa; c) providing a pair of opposing LDD regions within the semiconductive mesa, the respective LDD regions running along one of the mesa walls; and d) providing source and drain diffusion regions within the bulk semiconductor substrate floor which respectively interconnect with the opposing LDD regions of the mesa. NMOS field effect transistors are also disclosed.Type: GrantFiled: February 13, 1997Date of Patent: February 24, 1998Assignee: Micron Technology, Inc.Inventor: Jeff Zhiqiang Wu