Patents by Inventor Jeffery Boles

Jeffery Boles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficiently enqueuing workloads from user mode to hardware across privilege domains
    Patent number: 10424043
    Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Joseph Koston, Ankur Shah, Murali Ramadoss, Jeffery Boles, Balaji Vembu
  • Method and apparatus for efficient submission of workload to a high performance graphics sub-system
    Patent number: 10410311
    Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Kritika Bala, Murali Ramadoss, Hema Nalluri, Jeffery Boles, Jeffrey Frizzell, Joseph Koston
  • Method and Apparatus for Efficient Submission of Workload to a High Performance Graphics Sub-System
    Publication number: 20170256019
    Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 7, 2017
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Kritika Bala, Murali Ramadoss, Hema Nalluri, Jeffery Boles, Jeffrey Frizzell, Joseph Koston