Patents by Inventor Jeffrey A. Stuecheli
Jeffrey A. Stuecheli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860707Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.Type: GrantFiled: February 15, 2023Date of Patent: January 2, 2024Assignee: International Business Machines CorporationInventors: Brian Thomas Vanderpool, Gerald Mark Grabowski, Jeffrey A. Stuecheli, Michael Stephen Floyd, Matthew A. Cooke
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Patent number: 11693776Abstract: A processing unit includes a processor core and an associated cache memory. The cache memory establishes a reservation of a hardware thread of the processor core for a store target address and services a store-conditional request of the processor core by conditionally updating the shared memory with store data based on the whether the hardware thread has a reservation for the store target address. The cache memory receives a hint associated with the store-conditional request indicating an intent of the store-conditional request. The cache memory protects the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request. The cache memory establishes a first duration for the protection window extension based on the hint having a first value and establishes a different second duration for the protection window extension based on the hint having a different second value.Type: GrantFiled: June 18, 2021Date of Patent: July 4, 2023Assignee: International Business Machines CorporationInventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Jeffrey A. Stuecheli
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Publication number: 20230195202Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Inventors: Brian Thomas Vanderpool, Gerald Mark Grabowski, Jeffrey A. Stuecheli, Michael Stephen Floyd, Matthew A. Cooke
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Patent number: 11625087Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.Type: GrantFiled: August 28, 2021Date of Patent: April 11, 2023Assignee: International Business Machines CorporationInventors: Brian Thomas Vanderpool, Gerald Mark Grabowski, Jeffrey A. Stuecheli, Michael Stephen Floyd, Matthew A. Cooke
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Publication number: 20230063992Abstract: A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.Type: ApplicationFiled: August 18, 2021Publication date: March 2, 2023Inventors: HUGH SHEN, GUY L. GUTHRIE, JEFFREY A. STUECHELI, LUKE MURRAY, ALEXANDER MICHAEL TAFT, BERNARD C. DRERUP, DEREK E. WILLIAMS
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Publication number: 20230062546Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.Type: ApplicationFiled: August 28, 2021Publication date: March 2, 2023Inventors: Brian Thomas Vanderpool, Gerald Mark Grabowski, Jeffrey A. Stuecheli, Michael Stephen Floyd, Matthew A. Cooke
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Publication number: 20230044350Abstract: A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.Type: ApplicationFiled: August 4, 2021Publication date: February 9, 2023Inventors: BERNARD C. DRERUP, GUY L. GUTHRIE, JEFFREY A. STUECHELI, ALEXANDER MICHAEL TAFT, DEREK E. WILLIAMS
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Patent number: 11573902Abstract: A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.Type: GrantFiled: August 18, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Hugh Shen, Guy L. Guthrie, Jeffrey A. Stuecheli, Luke Murray, Alexander Michael Taft, Bernard C. Drerup, Derek E. Williams
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Publication number: 20230036054Abstract: A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: DEREK E. WILLIAMS, GUY L. GUTHRIE, William J. Starke, Jeffrey A. Stuecheli
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Patent number: 11561900Abstract: A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.Type: GrantFiled: August 4, 2021Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Bernard C. Drerup, Guy L. Guthrie, Jeffrey A. Stuecheli, Alexander Michael Taft, Derek E. Williams
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Patent number: 11537519Abstract: A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.Type: GrantFiled: July 29, 2021Date of Patent: December 27, 2022Assignee: International Business Machines CorporationInventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, David Campbell, Bryan Lloyd, Samuel David Kirchhoff, Jeffrey A. Stuecheli
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Publication number: 20220405202Abstract: A processing unit includes a processor core and an associated cache memory. The cache memory establishes a reservation of a hardware thread of the processor core for a store target address and services a store-conditional request of the processor core by conditionally updating the shared memory with store data based on the whether the hardware thread has a reservation for the store target address. The cache memory receives a hint associated with the store-conditional request indicating an intent of the store-conditional request. The cache memory protects the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request. The cache memory establishes a first duration for the protection window extension based on the hint having a first value and establishes a different second duration for the protection window extension based on the hint having a different second value.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: DEREK E. WILLIAMS, GUY L. GUTHRIE, HUGH SHEN, JEFFREY A. STUECHELI
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Patent number: 11449489Abstract: A technique for operating a data processing system that implements a split transaction coherency protocol that has an address tenure and a data tenure includes receiving, at a data source, a command (that includes an address tenure for requested data) that is issued from a data sink. The data source issues a response that indicates data associated with the address tenure is available to be transferred to the data sink during a data tenure. In response to determining that the data is available subsequent to issuing the response, the data source issues a first data packet to the data sink that includes the data during the data tenure. In response to determining that the data is not available subsequent to issuing the response, the data source issues a second data packet to the data sink that includes a data header that indicates the data is unavailable.Type: GrantFiled: November 9, 2017Date of Patent: September 20, 2022Assignee: International Business Machines CorporationInventors: Bernard C. Drerup, Guy L. Guthrie, Michael S. Siegel, Jeffrey A. Stuecheli
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Patent number: 11341060Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: GrantFiled: August 11, 2020Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Patent number: 11269561Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: December 21, 2020Date of Patent: March 8, 2022Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
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Patent number: 11263151Abstract: Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.Type: GrantFiled: July 29, 2020Date of Patent: March 1, 2022Assignee: International Business Machines CorporationInventors: David Campbell, Bryan Lloyd, David A. Hrusecky, Kimberly M. Fernsler, Jeffrey A. Stuecheli, Guy L. Guthrie, Samuel David Kirchhoff, Robert A. Cordes, Michael J. Mack, Brian Chen
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Publication number: 20220050787Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Publication number: 20220035748Abstract: Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Inventors: David Campbell, Bryan Lloyd, David A. Hrusecky, Kimberly M. Fernsler, Jeffrey A. Stuecheli, Guy L. Guthrie, SAMUEL DAVID KIRCHHOFF, Robert A. Cordes, Michael J. Mack, Brian Chen
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Patent number: 11113204Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory.Type: GrantFiled: April 18, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 11042325Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: August 5, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell