Abstract: The present disclosure introduces an integrated circuit (IC) device that includes a plurality of metal features in a first metal layer over and electrically connected to a semiconductor substrate, an intermetal dielectric (IMD) layer over the first metal layer, and a second metal layer over the first metal layer and electrically isolated from the first metal layer by the IMD layer. The second metal layer includes a plurality of thermal contacts separated by portions of a top dielectric layer. Each thermal contact has an upper surface with a dielectric-free area.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: An example method includes forming and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad; forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, wherein the first photoresist layer is not over the first bond pad and etching the second dielectric layer to a depth of 5 to 15% of a thickness of the first dielectric layer and the second dielectric layer; etching the first dielectric layer and second dielectric layer using a second photoresist layer to a depth of 20 to 25%; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer, such that an area of the dielectric layer exposed by the third opening adjacent to the bond pad is between 3-5 ?m thick.

Abstract: A system and method for vertically-oriented, modular, automated, emissions-controlled composting. In a preferred embodiment, the system and method involve construction of a vertically-oriented set of composting modules comprising a receiving and offloading level, one or more composting bay levels, a feedstock staging level, a biofilter level, a vertical conveyor for uploading feedstock to the feedstock staging level, a freight and personnel elevator, and a leachate tank. This composting system and method reduces the land area required for composting, increases the capture of emissions from composting, and reduces the labor-intensive and heavy-equipment-intensive nature of current methods.

Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: A sensor includes a sensing element, a first pair of lead wires, a second pair of lead wires, a grommet, and a shell. The first pair of lead wires is fixed to the sensing element and configured to receive signals from the sensing element. The second pair of lead wires is electrically connected to the first pair of lead wires at a joint. The second pair of lead wires is configured to receive signals from the first pair of lead wires. The grommet houses the joint, a portion of the first pair of lead wires, and a portion of the second pair of lead wires. The shell houses the sensing element, the first pair of lead wires, and the grommet. The shell engages and deforms the grommet to seal an interior space defined by the shell.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: A sensor assembly and a refrigerant sensing system for air conditioning systems can include a sensor controller, a sensor electrically connected to the sensor controller and configured to output sensor data to the sensor controller, and a housing having an interior space enclosing the sensor controller and the sensor. The housing includes a first end and a second end and a barrier disposed between the first end and the second end sealingly separating the interior space. The first end supports the sensor and includes a plurality of openings exposing the sensor to an external environment. The second end supports the sensor controller and substantially prevents the sensor controller from being exposed to the external environment.

Abstract: A sensor assembly includes a controller, a sensor, and a housing. The housing encloses the controller and sensor and includes a body supporting the controller and a head supporting the sensor. The body prevents exposure of the controller to an external environment, and the head includes slots enabling exposure of the sensor to the external environment.

Abstract: An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.

Abstract: A refrigerant sensor assembly having a body including an outer surface. A recessed portion may be included on or formed in the body. The recessed portion may include the outer surface. The recessed portion may have a curved, generally convex shape having an upwardly facing open end and a lowest portion or bottom opposite the upwardly facing open end. A sensor suitable for detecting the presence of a refrigerant (e.g., a lower GWP refrigerant and/or an A2L refrigerant) and/or certain specified chemical compounds (e.g., hydrofluorocarbons) (e.g., a refrigerant sensor) may be disposed at the bottom of the recessed portion. Alternatively an enclosed collection space may be located beneath the recessed portion. An aperture or opening may be formed through the recessed portion and may adjoin the recessed portion with the collection space. A refrigerant sensor alternatively may be disposed in the collection space.

Abstract: A sensor assembly including a housing having an inlet an outlet and an interior space generally closed from an environment external to the sensor assembly. The interior space of the housing can include an inlet zone, a central zone and an outlet zone. A baffle can be disposed within the central zone of the interior space of the housing and be located between the inlet zone and the outlet zone and nearer to the inlet zone than to the outlet zone. The baffle can extend downwardly from an upper side of the housing. A gas sensor that can be operable to detect a presence of a lower GWP refrigerant can be disposed in the outlet zone of the interior space of the housing. The housing includes a door in a lower side of the housing in the central zone of the housing.

Abstract: A storage system comprising: a pair of rails, comprising a first rail and a second rail; rail mounts for mounting the first and second rails in an at least generally parallel orientation in position on or to a supporting surface; a storage frame defining a storage space for storing items therein; a first connector for connecting the storage frame to the first rail; and a second connector for connecting the storage frame to the second rail; wherein the first connector includes a first connector rail part and a first connector frame part, with the first connector rail part provided on the first rail; and the first connector frame part provided on the storage frame, with one of the first connector rail part and the first connector frame part slidably receivable in the other of the first connector rail part and the first connector frame part.

Abstract: A storage system, comprising: a frame, the frame comprising two opposing frame side walls, a frame rear wall, a frame top wall and a frame base, which collectively define a drawer receiving space; the frame having a front opening; a drawer receivable in the drawer receiving space through the front opening; the drawer comprising first and second opposing drawer side walls, a drawer base, a drawer front wall and a drawer rear wall, which collectively define a drawer storage space, the drawer having a top opening for receiving contents into the drawer storage space; a drawer position retainer for releasably retaining the drawer in any one of at least two drawer positions relative to the frame, the at least two drawer positions comprising: a closed position, wherein the drawer is at least substantially received within the frame; and a partially open position, wherein the drawer is partially received within the frame; and an actuator mounted to or adjacent the drawer front wall for manually actuating the drawer po

Abstract: An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.

Abstract: An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.

Abstract: An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.

Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.