Patents by Inventor Jeffrey A. Wilcox

Jeffrey A. Wilcox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060190751
    Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
    Type: Application
    Filed: February 14, 2006
    Publication date: August 24, 2006
    Inventors: Jeffrey Wilcox, Noam Yosef
  • Publication number: 20060080461
    Abstract: A method is described that, in order to change an operational state of a resource within a computing system that is shared by components of the computing system so that the computing system's power consumption is altered, sends a packet over one or more nodal hops within a packet based network within the computing system. The packet contains information pertaining to the power consumption alteration.
    Type: Application
    Filed: June 2, 2004
    Publication date: April 13, 2006
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, Bernard Lint, Lance Hacking
  • Publication number: 20060034295
    Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
    Type: Application
    Filed: May 21, 2004
    Publication date: February 16, 2006
    Inventors: Naveen Cherukuri, Aaron Spink, Phanindra Mannava, Tim Frodsham, Jeffrey Wilcox, Sanjay Dabral, David Dunning, Theodore Schoenborn
  • Publication number: 20050273633
    Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 8, 2005
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, David Poisner, Bernard Lint, Lance Hacking
  • Publication number: 20050273635
    Abstract: Methods and apparatuses for coordination of power state management in and electronic system.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 8, 2005
    Inventors: Jeffrey Wilcox, Shivnandan Kaushik, Stephen Gunther, Devadatta Bodas, Siva Ramakrishnan, David Poisner, Lance Hacking
  • Publication number: 20050262365
    Abstract: A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a pervious period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 24, 2005
    Inventors: Bernard Lint, Alon Naveh, Shivnandan Kaushik, Jeffrey Wilcox, Lance Hacking, Ping Sager, Kushagra Vaid, Todd Dutton
  • Publication number: 20050262368
    Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 24, 2005
    Inventors: Naveen Cherukuri, Jeffrey Wilcox, Sanjay Dabral, Phanindra Mannava, Aaron Spink, David Dunning, Tim Frodsham, Theodore Schoenborn
  • Publication number: 20050259599
    Abstract: A technique to perform virtualization of lanes within a common system interface (CSI) link. More particularly, embodiments described herein relate to virtualizing interconnective paths between two or more electronic devices residing in an electronic network.
    Type: Application
    Filed: July 13, 2004
    Publication date: November 24, 2005
    Inventors: Naveen Cherukuri, Jeffrey Wilcox, Sanjay Dabral, David Dunning, Tim Frodsham, Theodore Schoenborn
  • Publication number: 20050179293
    Abstract: A seat suspension has a base and a seat support. A foundation extends upwardly at a forward portion of the base. A pair of panels hingedly extends from the foundation, with a spring between each panel and the base. In one embodiment, the panels are hinged to the foundation by a living hinge. In another embodiment, the panels are formed of glass springs, wherein each panel comprises one arm of the spring. In another embodiment, the seat suspension is adjustable.
    Type: Application
    Filed: April 29, 2005
    Publication date: August 18, 2005
    Inventor: Jeffrey Wilcox
  • Publication number: 20050086420
    Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffers coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.
    Type: Application
    Filed: November 19, 2004
    Publication date: April 21, 2005
    Inventors: Jeffrey Wilcox, Opher Kahn, Alon Naveh
  • Patent number: 6532547
    Abstract: A redundant peripheral device subsystem in a computer system is disclosed including first and second peripheral device controllers. First and second peripheral device busses are coupled to the first and second peripheral device controllers, respectively. A controllable switch is coupled between the first and second peripheral device busses. The controllable switch either isolates the first and second peripheral device busses from each other, or joins them into a single peripheral device bus.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: March 11, 2003
    Assignee: EMC Corporation
    Inventor: Jeffrey A. Wilcox
  • Patent number: 6185634
    Abstract: An address triggered DMA controller includes a DMA engine for controlling transfer of data between an external device and locations in a memory designated by respective addresses. Such a DMA controller also includes a DMA monitor for monitoring the respective addresses, and if one of the respective addresses matches a predetermined value, generating a signal to indicate a match.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: February 6, 2001
    Assignee: EMC Corporation
    Inventor: Jeffrey Wilcox
  • Patent number: 6107855
    Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: August 22, 2000
    Assignee: EMC Corporation
    Inventor: Jeffrey Wilcox
  • Patent number: 5886557
    Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: March 23, 1999
    Assignee: EMC Corporation
    Inventor: Jeffrey Wilcox
  • Patent number: 5798961
    Abstract: A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: August 25, 1998
    Assignee: EMC Corporation
    Inventors: Christopher A. Heyden, Jeffrey S. Kinne, Mitchell N. Rosich, Jeffrey A. Wilcox, Jeffrey L. Winkler
  • Patent number: 5594862
    Abstract: An XOR controller which is capable of performing the XOR operations necessary to generate a new parity value corresponding to new data being written to a disk storage device from a host computer without the intervention of the storage subsystem microprocessor. In one embodiment the storage subsystem microprocessor controls the loading of the new data from the host and old data and parity from a disk storage device into cache memory, if such data is not already in cache memory, and creates the appropriate data structures. The storage subsystem microprocessor then loads the XOR controller with a pointer to a table in cache memory containing information needed by the XOR controller to perform the XOR operations. The XOR controller, upon completion of the XOR operations on all the data, informs the storage subsystem microprocessor of such completion. Thereafter, the microprocessor causes the new data and new parity to be written to the disk storage device from the cache memory.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: January 14, 1997
    Assignee: EMC Corporation
    Inventors: Jeffrey L. Winkler, Jeffrey A. Wilcox
  • Patent number: 5586300
    Abstract: A controller capable of performing the flexible addressing of memory modules. In one embodiment, involving cache memory, a cache controller maintains, for each slot in cache memory, a read base address and a write base address for the slot and certain characteristics of the SIMM residing in the slot. The use of separate write and read addresses permits more than one cache memory SIMM to be written to with a single write address and permits cache memory to be non-contiguous and thus more robust with respect to SIMM failures. The maintenance of a table of SIMM characteristics permits volatile and non-volatile SIMMs to be used together in cache memory.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: December 17, 1996
    Assignee: EMC Corporation
    Inventors: Jeffrey A. Wilcox, Jeffrey L. Winkler