Patents by Inventor Jeffrey Alan Knight
Jeffrey Alan Knight has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7098136Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.Type: GrantFiled: August 20, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Ronald Clothier, Jeffrey Alan Knight, Robert David Sebesta
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Patent number: 6841228Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: GrantFiled: September 3, 2003Date of Patent: January 11, 2005Assignee: International Business Machines CorporationInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Patent number: 6815709Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.Type: GrantFiled: May 23, 2001Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Ronald Clothier, Jeffrey Alan Knight, Robert David Sebesta
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Publication number: 20040081810Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: ApplicationFiled: September 3, 2003Publication date: April 29, 2004Applicant: International Business MachinesInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Patent number: 6663786Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: GrantFiled: June 14, 2001Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Publication number: 20020192439Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: ApplicationFiled: June 14, 2001Publication date: December 19, 2002Applicant: International Business Machines CorporationInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Publication number: 20020177006Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: Ronald Clothier, Jeffrey Alan Knight, Robert David Sebesta
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Patent number: 6351030Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.Type: GrantFiled: March 25, 1999Date of Patent: February 26, 2002Assignee: International Business Machines CorporationInventors: Ross Downey Havens, Robert Maynard Japp, Jeffrey Alan Knight, Mark David Poliks, Anne M. Quinn
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Publication number: 20010011773Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.Type: ApplicationFiled: March 25, 1999Publication date: August 9, 2001Inventors: ROSS DOWNEY HAVENS, ROBERT MAYNARD JAPP, JEFFREY ALAN KNIGHT, MARK DAVID POLIKS, ANNE M. QUINN, RONALD D. QUINN
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Patent number: 6038137Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.Type: GrantFiled: June 6, 1997Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Ashwinkumar Chinuprasad Bhatt, Subahu Dhirubhai Desai, Thomas Patrick Duffy, Jeffrey Alan Knight
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Patent number: 5888850Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.Type: GrantFiled: September 29, 1997Date of Patent: March 30, 1999Assignee: International Business Machines CorporationInventors: Ross Downey Havens, Robert Maynard Japp, Jeffrey Alan Knight, Mark David Poliks, Anne M. Quinn, deceased
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Patent number: 5869356Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.Type: GrantFiled: March 17, 1998Date of Patent: February 9, 1999Assignee: International Business Machines CorporationInventors: James W. Fuller, Jr., Mary Beth Fletcher, Joseph Alphonse Kotylo, Jeffrey Alan Knight, David Michael Passante, Allen F. Moring
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Patent number: 5817405Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.Type: GrantFiled: February 4, 1997Date of Patent: October 6, 1998Assignee: International Business Machines CorporationInventors: Anikumar Chinuprasad Bhatt, Ashwinkumar Chinuprasad Bhatt, Robert Jeffrey Day, Thomas Patrick Duffy, Jeffrey Alan Knight, Richard William Malek, Voya Rista Markovich
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Patent number: 5798909Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.Type: GrantFiled: February 15, 1995Date of Patent: August 25, 1998Assignee: International Business Machines CorporationInventors: Ashwinkumar Chinuprasad Bhatt, Subahu Dhirubhai Desai, Thomas Patrick Duffy, Jeffrey Alan Knight
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Patent number: 5784260Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.Type: GrantFiled: May 29, 1996Date of Patent: July 21, 1998Assignee: International Business Machines CorporationInventors: James W. Fuller, Jr., Mary Beth Fletcher, Joseph Alphonse Kotylo, Jeffrey Alan Knight, David Michael Passante, Allen F. Moring
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Patent number: 5724232Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.Type: GrantFiled: May 21, 1996Date of Patent: March 3, 1998Assignee: International Business Machines CorporationInventors: Ashwinkumar Chinuprasad Bhatt, Subahu Dhirubhai Desai, Thomas Patrick Duffy, Jeffrey Alan Knight
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Patent number: 5707893Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.Type: GrantFiled: December 1, 1995Date of Patent: January 13, 1998Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Ashwinkumar Chinuprasad Bhatt, Robert Jeffrey Day, Thomas Patrick Duffy, Jeffrey Alan Knight, Richard William Malek, Voya Rista Markovich