Abstract: A decimation filtering circuit for performing a decimation operation with a decimation factor of M in a pipelined structure. A finite impulse response ("FIR") filtering of N taps for achieving a desired frequency response is designed to have an integral ratio of N/M. A total of N/M processing stages is connected in series to accumulate filtered data based on data samples of an input signal and predetermined FIR coefficients. Each of the N/M processing stages produces an accumulated output in every other M accumulations for M input data samples.

Abstract: An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.