Patents by Inventor Jeffrey C. Lam

Jeffrey C. Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gamma groove arrays for interconnecting and mounting devices
    Patent number: 10656362
    Abstract: Devices with gamma (?) grooves are disclosed. The ? grooves can be used to form optical fiber arrays. The ? grooves can be formed using a dry etch, such as RIE, by modifying resist features of an etch mask to have convex curved sidewalls. The profile of the resist features is transferred to the substrate by the dry etch to form the ? grooves. The ? grooves are formed without K containing etchants, avoiding K+ ions contamination of process tools as well as health issues caused by handling alkali containing devices.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yamin Huang, Bo Liu, Zhihong Mai, Jeffrey C Lam
  • GAMMA GROOVE ARRAYS FOR INTERCONNECTING AND MOUNTING DEVICES
    Publication number: 20190204525
    Abstract: Devices with gamma (?) grooves are disclosed. The ? grooves can be used to form optical fiber arrays. The ? grooves can be formed using a dry etch, such as RIE, by modifying resist features of an etch mask to have convex curved sidewalls. The profile of the resist features is transferred to the substrate by the dry etch to form the ? grooves. The ? grooves are formed without K containing etchants, avoiding K+ ions contamination of process tools as well as health issues caused by handling alkali containing devices.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 4, 2019
    Inventors: Yamin HUANG, Bo LIU, Zhihong MAI, Jeffrey C. LAM
  • Laser-enhanced chemical etching of nanotips
    Patent number: 9128117
    Abstract: A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 8, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: ZhiHong Mai, Jeffrey C. Lam, Mohammed Khalid Bin Dawood, Tsu Hau Ng
  • LASER-ENHANCED CHEMICAL ETCHING OF NANOTIPS
    Publication number: 20140242805
    Abstract: A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates.
    Type: Application
    Filed: December 4, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: ZhiHong MAI, Jeffrey C. LAM, Mohammed Khalid BIN DAWOOD, Tsu Hau NG
  • Integrated circuit system with through silicon via and method of manufacture thereof
    Patent number: 8536705
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20120205806
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pradeep Ramachandramurthy YELEHANKA, Denise TAN, Chung Meng LEK, Thomas THIAM, Jeffrey C. LAM, Liang-Choo HSIA
  • Integrated circuit system with through silicon via and method of manufacture thereof
    Patent number: 8236688
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 7, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • Integrated circuit system employing backside energy source for electrical contact formation
    Patent number: 8158513
    Abstract: A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 17, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhihong Mai, Suey Li Toh, Pik Kee Tan, Jeffrey C. Lam, Liang-Choo Hsia
  • INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110237072
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Application
    Filed: June 13, 2011
    Publication date: September 29, 2011
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • Method of manufacture an integrated circuit system with through silicon via
    Patent number: 7960282
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: June 14, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20100297844
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Application
    Filed: May 21, 2009
    Publication date: November 25, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • INTEGRATED CIRCUIT SYSTEM EMPLOYING BACKSIDE ENERGY SOURCE FOR ELECTRICAL CONTACT FORMATION
    Publication number: 20100087061
    Abstract: A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 8, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Zhihong Mai, Suey Li Toh, Pik Kee Tan, Jeffrey C. Lam, Liang-Choo Hsia