Patents by Inventor Jeffrey C. Solomon

Jeffrey C. Solomon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory module with a circuit providing load isolation and memory domain translation
    Patent number: 7636274
    Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 22, 2009
    Assignee: Netlist, Inc.
    Inventors: Jeffrey C Solomon, Jayesh R Bhakta
  • Memory module decoder
    Patent number: 7619912
    Abstract: A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 17, 2009
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon
  • MEMORY MODULE WITH A CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION
    Publication number: 20090201711
    Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.
    Type: Application
    Filed: March 20, 2009
    Publication date: August 13, 2009
    Applicant: Netlist, Inc.
    Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
  • Memory module with a circuit providing load isolation and memory domain translation
    Patent number: 7532537
    Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: May 12, 2009
    Assignee: Netlist, Inc.
    Inventors: Jeffrey C. Solomon, Jayesh R. Bhakta
  • Memory module decoder
    Patent number: 7289386
    Abstract: A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: October 30, 2007
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Jeffrey C. Solomon