Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.