Abstract: An automatic gain control circuit includes an input gain stage for receiving and amplifying an analog input signal; an analog-to-digital converter for receiving the amplified analog input signal and providing a digital output signal; and an overload management module. The overload management module is arranged to receive the digital output signal; determine therefrom whether the received, amplified analog input signal exceeds an operating range of the analog-to-digital converter; and provide a first control signal to the input gain stage to adjust a gain of the input gain stage in response thereto.

Abstract: An automatic gain control circuit includes an input gain stage for receiving and amplifying an analog input signal; an analog-to-digital converter for receiving the amplified analog input signal and providing a digital output signal; and an overload management module. The overload management module is arranged to receive the digital output signal; determine therefrom whether the received, amplified analog input signal exceeds an operating range of the analog-to-digital converter; and provide a first control signal to the input gain stage to adjust a gain of the input gain stage in response thereto.

Abstract: A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.

Abstract: An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Abstract: A continuous-time sigma-delta analog-to-digital converter includes a first integrator stage to integrate a difference between a first differential signal derived from a differential analog input signal and a second differential signal derived from a quantized output signal, a quantizer and a low pass filter. The first integrator stage has a differential operational amplifier, first, second, third, and fourth input resistors, and a first pair of integrating capacitors. The differential analog input signal is received at first and second input nodes of the converter. The first and third input resistors are coupled in series between the first input node and a first input of the operational amplifier. The second and fourth input resistors are coupled in series between the second input node and a second input of the operational amplifier. The first and second input resistors are coupled to the third and fourth input resistors, respectively.

Abstract: A continuous-time sigma-delta analog-to-digital converter includes a first integrator stage to integrate a difference between a first differential signal derived from a differential analog input signal and a second differential signal derived from a quantized output signal, a quantizer and a low pass filter. The first integrator stage has a differential operational amplifier, first, second, third, and fourth input resistors, and a first pair of integrating capacitors. The differential analog input signal is received at first and second input nodes of the converter. The first and third input resistors are coupled in series between the first input node and a first input of the operational amplifier. The second and fourth input resistors are coupled in series between the second input node and a second input of the operational amplifier. The first and second input resistors are coupled to the third and fourth input resistors, respectively.

Abstract: An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Abstract: A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.