Patents by Inventor Jeffrey Chee Wei-Lun

Jeffrey Chee Wei-Lun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6709912
    Abstract: A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew-Hoe Ang, Jeffrey Chee Wei-Lun, Wenhe Lin, Jia Zhen Zheng