Patents by Inventor Jeffrey Cook
Jeffrey Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240183693Abstract: An AMI/AMR in-ground meter box, including first and second side panels, each having an interior side and an exterior side; and first and second end panels, each having an interior side and an exterior side; wherein each of said side panels and end panels include a generally rectangular planar portion having a top edge, a bottom edge, a first interlocking end having a plurality of male elements and female slots, an arcuate second end having a 90-degree bend which forms a corner of the assembled meter box and terminating in an interlocking end having a plurality of male elements and female slots configured to interlock with paired male elements and female slots in said first interlocking end and with an improved adjustable bracket channel assembly for interior support.Type: ApplicationFiled: February 16, 2024Publication date: June 6, 2024Applicant: NICOR, INC.Inventor: JEFFREY A. COOK
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Publication number: 20240120657Abstract: An antenna and antenna enclosure including a housing having a cylindrical first portion defining a hollow interior volume with an inner diameter, a cylindrical second portion defining a hollow interior portion having an inner diameter greater than the inner diameter of the first portion, and a disk disposed inside the second portion and defining a central hole. A rod is disposed in and extends through the central hole of the disk and is captured in the hollow interior volume of the cylindrical first portion. The rod defines a central opening and abuts an inner surface of the disk. A wire is arranged inside the central opening, and a cap covers the hollow interior of the cylindrical portion and engages the housing. A circuit board for the antenna is disposed on underside of the cap and connects to the wire.Type: ApplicationFiled: July 20, 2022Publication date: April 11, 2024Applicant: Nicor, Inc.Inventor: Jeffrey A. COOK
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Publication number: 20240109808Abstract: Disclosed herein is a transportable bio-cement comprising a desiccated microorganism package; where the microorganism package comprises one or more microorganisms; a first binder, where the first binder is produced by the microorganism; and where the microorganism has protected itself by a layer of the first binder; where the transportable bio-cement is devoid of moisture. Disclosed herein too is a method of manufacturing a transportable dry composition comprising blending together a microorganism package; a nutrient; and a liquid; activating the microorganism package to produce a first binder; subjecting the microorganism package to desiccation to form a transportable bio-cement; and blending the transportable bio-cement with an aggregate to form a bio-concrete; where the aggregate comprises a substrate, a second binder, and a liquid.Type: ApplicationFiled: September 18, 2023Publication date: April 4, 2024Inventors: Wilfred V. Srubar, III, Sherri Cook, Jeffrey Cameron, Mija Hubler, Stephen Bell, Linfei Li
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Patent number: 11940468Abstract: An AMI/AMR in-ground meter box, including first and second side panels, each having an interior side and an exterior side; and first and second end panels, each having an interior side and an exterior side; wherein each of said side panels and end panels include a generally rectangular planar portion having a top edge, a bottom edge, a first interlocking end having a plurality of male elements and female slots, an arcuate second end having a 90-degree bend which forms a corner of the assembled meter box and terminating in an interlocking end having a plurality of male elements and female slots configured to interlock with paired male elements and female slots in said first interlocking end.Type: GrantFiled: February 5, 2021Date of Patent: March 26, 2024Assignee: NICOR, INC.Inventor: Jeffrey A. Cook
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Publication number: 20240057605Abstract: New formulations of clomazone are provided, as well as new methods for making formulations of clomazone. The new formulations provide improved efficacy, decreased volatility, and/or increased loading of clomazone over the clomazone formulations in the prior art.Type: ApplicationFiled: September 14, 2023Publication date: February 22, 2024Inventors: Hong LIU, Michael R. Welsh, Paul Nicholson, Jeffrey A. Cook, Catherine Ranin, Sandra L. Shinn, Robert F. Pepper
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Patent number: 11909111Abstract: An assembly includes: a) a housing comprising a floor, a ceiling, a rear wall, a front wall, and opposed side walls that define a cavity, wherein the side walls include illuminable informational markings; an antenna; c) a radio residing in the cavity of the housing connected with the antenna; and d) a power source attached to the radio; wherein the power source is employed to illuminate the informational markings.Type: GrantFiled: January 17, 2020Date of Patent: February 20, 2024Assignee: COMMSCOPE TECHNOLOGIES LLCInventors: Julian Colapietro, Charles John Mann, Michael Fabbri, Jeffrey Cook
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Publication number: 20230396015Abstract: An electrical backshell that includes a strain relief having a flexible neck connected to a jacketed data cable proximate a terminal end of the data cable, and a cylindrical portion integral with said flexible neck; a base connector configured to accept and accommodate the terminal end of the data cable; a coupling nut configured to connect with said base connector and to engage said strain relief and to bring said cylindrical portion of said strain relief into sealing engagement with said base connector, wherein when assembled, said electrical backshell provides waterproof protection for electrical connectors in underground utility meter boxes.Type: ApplicationFiled: May 26, 2023Publication date: December 7, 2023Applicant: Nicor, Inc.Inventor: Jeffrey A. Cook
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Publication number: 20230315462Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315445Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315455Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315460Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315459Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315444Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315458Abstract: Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: Shreesha SRINATH, Jonathan PEARCE, David B. SHEFFIELD, Ching-Kai LIANG, Jeffrey COOK
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Publication number: 20230315461Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230315572Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
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Publication number: 20230053289Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.Type: ApplicationFiled: June 21, 2022Publication date: February 16, 2023Applicant: Intel CorporationInventors: Amit Bleiweiss, Anavai Ramesh, Asit Mishra, Deborah Marr, Jeffrey Cook, Srinivas Sridharan, Eriko Nurvitadhi, Elmoustapha Ould-Ahmed-Vall, Dheevatsa Mudigere, Mohammad Ashraf Bhuiyan, Md Faijul Amin, Wei Wang, Dhawal Srivastava, Niharika Maheshwari
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Patent number: 11379229Abstract: An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.Type: GrantFiled: August 7, 2020Date of Patent: July 5, 2022Assignee: INTEL CORPORATIONInventors: Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey Cook, Debbie Marr, Abhijit Davare, Asit Mishra, Steven Burns, Desmond A. Kirkpatrick, Andrey Ayupov, Anton Alexandrovich Sorokin, Eriko Nurvitadhi
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Patent number: 11373088Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.Type: GrantFiled: December 30, 2017Date of Patent: June 28, 2022Assignee: INTEL CORPORATIONInventors: Amit Bleiweiss, Anavai Ramesh, Asit Mishra, Deborah Marr, Jeffrey Cook, Srinivas Sridharan, Eriko Nurvitadhi, Elmoustapha Ould-Ahmed-Vall, Dheevatsa Mudigere, Mohammad Ashraf Bhuiyan, Md Faijul Amin, Wei Wang, Dhawal Srivastava, Niharika Maheshwari
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Patent number: D1016327Type: GrantFiled: February 9, 2021Date of Patent: February 27, 2024Assignee: Tesseract Ventures, LLCInventors: John Boucard, David Starr, Jeffrey Chiu, Greg Lorett, Spencer Cook, Jason Harrell