Patents by Inventor Jeffrey Curtis Hedrick
Jeffrey Curtis Hedrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7695776Abstract: The present invention related to an improved structure of an optically transparent element that can be used in optical scanners, supermarket scanners, lenses for eyeglasses, etc. The application of oxynitride PECVD films provide good hardness and optical transparency. Such films displaying these physical properties are extremely useful as a scratch resistant coatings in lenses and systems in which an article contacts a transparent surface, such as in scanners and in environments in which intermittent, environmental contact occurs such as in displays for computers and suchlike and in liquid crystal displays, touch displays and compact disks.Type: GrantFiled: May 23, 2008Date of Patent: April 13, 2010Assignee: International Business Machines Corp.Inventors: Jeffrey Curtis Hedrick, David Andrew Lewis, Stanley Joseph Whitehair
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Publication number: 20080286493Abstract: The present invention related to an improved structure of an optically transparent element that can be used in optical scanners, supermarket scanners, lenses for eyeglasses, etc. The application of oxynitride PECVD films provide good hardness and optical transparency. Such films displaying these physical properties are extremely useful as a scratch resistant coatings in lenses and systems in which an article contacts a transparent surface, such as in scanners and in environments in which intermitent, environmental contact occurs such as in displays for computers and suchlike and in liquid crystal displays, touch displays and compact disks.Type: ApplicationFiled: May 23, 2008Publication date: November 20, 2008Inventors: Jeffrey Curtis Hedrick, David Andrew Lewis, Stanley Joseph Whitehair
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Patent number: 7378146Abstract: The present invention related to an improved structure of an optically transparent element that can be used in optical scanners, supermarket scanners, lenses for eyeglasses, etc. The application of oxynitride PECVD films provide good hardness and optical transparency. Such films displaying these physical properties are extremely useful as a scratch resistant coatings in lenses and systems in which an article contacts a transparent surface, such as in scanners and in environments in which intermittent, environmental contact occurs such as in displays for computers and suchlike and in liquid crystal displays, touch displays and compact disks.Type: GrantFiled: August 5, 1998Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Jeffrey Curtis Hedrick, David Andrew Lewis, Stanley Joseph Whitehair
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Patent number: 7098476Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: GrantFiled: September 24, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
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Patent number: 7084479Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: GrantFiled: December 8, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Venkata Nitta, Sampath Purushothaman, Robert Rosenburg, Christy Sensenich Tyberg, Roy RongQing Yu
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Patent number: 6831366Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: GrantFiled: March 25, 2003Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Patent number: 6831364Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.Type: GrantFiled: August 1, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: 6815329Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: GrantFiled: April 2, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
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Patent number: 6737725Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.Type: GrantFiled: May 13, 2002Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Satyanarayana Venkata Nitta, Kevin S. Petrarca, Sampath Purushothaman, Katherine Lynn Saenger, Stanley Joseph Whitehair
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Patent number: 6730618Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.Type: GrantFiled: May 1, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Stephan Alan Cohen, Claudius Feger, Jeffrey Curtis Hedrick, Jane Margaret Shaw
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Patent number: 6724069Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.Type: GrantFiled: April 5, 2001Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
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Patent number: 6716742Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: GrantFiled: November 12, 2002Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Patent number: 6710450Abstract: An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics.Type: GrantFiled: February 28, 2001Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Patent number: 6677680Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics.Type: GrantFiled: February 28, 2001Date of Patent: January 13, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Publication number: 20030183937Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: ApplicationFiled: March 25, 2003Publication date: October 2, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Patent number: 6603204Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: GrantFiled: February 28, 2001Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Publication number: 20030075803Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: ApplicationFiled: November 12, 2002Publication date: April 24, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Publication number: 20030057414Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving as dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: ApplicationFiled: August 1, 2002Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: 6537908Abstract: A cost effective and simple method of patterning interconnect structures is provided in which spun-on materials are used as the hard mask. The use of spun-on materials for the hard mask ensures that the process is carried out in a single tool and it permits the use of a single curing step which is not typically employed in patterning processes wherein CVD hard masks are employed. The effective dielectric constant of the resultant structure is not significantly increased since the use of spin coating allows for selection of a polish stop layer (formed on a surface of a low-k dielectric) that has substantially the same dielectric constant as the underlying dielectric. In the present invention, the hard mask employed includes at least two spun-on dielectric materials that have different etch rates.Type: GrantFiled: February 28, 2001Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventors: Ann Rhea-Helene Fornof, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
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Publication number: 20020160600Abstract: A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of said silane-coupling agent on said substrate; (b) heating the substrate containing the coating of the silane-coupling agent at a temperature of about 90° C. or above so as to provide a surface containing Si—O bonds; (c) rinsing the heated substrate with a suitable solvent that is effective in removing any residual silane-coupling agent; and (d) applying a dielectric material to the rinsed surface containing the Si—O bonds.Type: ApplicationFiled: February 21, 2001Publication date: October 31, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew Robert Eckert, John C. Hay, Jeffrey Curtis Hedrick, Kang-Wook Lee, Eric Gerhard Liniger, Eva Erika Simonyi