Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: The invention relates to decoding utilizing image data. The image data can be received from a source. A processor can process the image data for decoding. Processing for decoding can be responsive to determined information. The format of a frame of image data may be recognized. The recognizing may include determining the source of the frame of image data. The recognizing may include determining a parameter associated with the frame of image data.

Abstract: The invention relates to decoding utilizing image data. The image data can be received from a source. A processor can process the image data for decoding. Processing for decoding can be responsive to determined information. The format of a frame of image data may be recognized. The recognizing may include determining the source of the frame of image data. The recognizing may include determining a parameter associated with the frame of image data.

Abstract: The invention relates to decoding utilizing image data. The image data can be received from a source. A processor can process the image data for decoding. A processing for decoding can be responsive to determined information.

Abstract: The invention relates to a microprocessor-based decoder board for an optical reader having in one embodiment a plurality of imaging modules that provide frames of image data having a plurality of formats. In one method for operating the decoder board of the invention, and a multiple imaging module reader comprising the decoder board, a frame of image data captured by a selected imaging module is decoded. The decoder board determines the format of the frame of image data from information about which of the plurality of imaging modules provided the frame of image data or from information about the frame of image data, activates as necessary a command to prepare the decoder board to decode the frame of image data according to the format provided by the imaging module, and performs the decoding.

Abstract: A multi-dimensional imaging device and method for automated exposure control that implement two distinct modules to control the exposure and gain settings in the imager so that processing can occur in a multi-tasking single CPU environment. The first module, referred to herein as the imager control module, controls the exposure and gain settings in the imager. The first module is typically implemented in a high priority routine, such as an interrupt service routine, to insure that module is executed on every captured frame. The second module, referred to herein as the histogram processing module, calculates a target contrast (the product of the targeted exposure and gain settings) based on feedback data from the first module and image data from memory. The second module is typically implemented in a low priority routine, such as a task level routine, to allow for the routine to be executed systematically in accordance with priority.

Abstract: The invention relates to a microprocessor-based decoder board for an optical reader having in one embodiment a plurality of imaging modules that provide frames of image data having a plurality of formats. In one method for operating the decoder board of the invention, and a multiple imaging module reader comprising the decoder board, a frame of image data captured by a selected imaging module is decoded. The decoder board determines the format of the frame of image data from information about which of the plurality of imaging modules provided the frame of image data or from information about the frame of image data, activates as necessary a command to prepare the decoder board to decode the frame of image data according to the format provided by the imaging module, and performs the decoding.

Abstract: An improved method and device for capturing image data benefits from having a single central processor execute the operating system, and the image capture, decode and processing programs. A method for capturing of image data comprises transmitting image data from an imager, assembling the image data, assigning a memory address to the assembled image data and transferring the assembled image data into system memory. This method is capable of central processing whereby the capturing of image data is executed via the main processor without having to invoke a dedicated processor or incorporate external components, such as additional PCBs, external digital signal processing or external data storage. Additionally, an imaging device comprises an image builder module that receives image data from the imager bus and assembles the data, and a transfer controller that initiates the image builder module and controls the transfer of image data into and out of memory.

Abstract: The invention is a microprocessor-based decoder board for an optical reader having a plurality of imaging modules that provide frames of image data having a plurality of formats. In one method for operating the decoder board of the invention, and a multiple imaging module reader comprising the decoder board, a frame of image data captured by a selected imaging module is decoded. The decoder board determines the format of the frame of image data from information about which of the plurality of imaging modules provided the frame of image data or from information about the frame of image data, activates as necessary a command to prepare the decoder board to decode the frame of image data according to the format provided by the imaging module, and performs the decoding.

Abstract: The invention is a method of manufacturing a microprocessor-based decoder board for an optical reader having a plurality of imaging modules that provide frames of image data having a plurality of formats. In one method for operating the decoder board of the invention, and a multiple imaging module reader comprising the decoder board, a frame of image data captured by a selected imaging module is decoded. The decoder board determines the format of the frame of image data from information about which of the plurality of imaging modules provided the frame of image data or from information about the frame of image data, activates as necessary a command to prepare the decoder board to decode the frame of image data according to the format provided by the imaging module, and performs the decoding.

Abstract: An imaging device and a method for implementing simultaneous image capture and image display update in an imaging device are provided. The imaging device of the present invention implements first and second image capture buffers within a memory module such that a first buffer captures image data from the imager while the second buffer displays the image on the imaging device display. A method for simultaneous image capture and image display update comprises capturing first-in-time image data to a first image capture buffer that is in communication with an imager, capturing second-in-time image data to a second image capture buffer that is in communication with an imager and displaying the first-in-time image data on a display while the image device captures the second-in time image data to the second image capture buffer.

Abstract: A multi-dimensional imaging device and method for automated exposure control that implement two distinct modules to control the exposure and gain settings in the imager so that processing can occur in a mult-tasking single CPU environment. The first module, referred to herein as the imager control module, controls the exposure and gain settings in the imager. The first module is typically implemented in a high priority routine, such as an interrupt service routine, to insure that module is executed on every captured frame. The second module, referred to herein as the histogram processing module, calculates a target contrast (the prduct of the targeted exposure and gain settings) based on feedback data from the first module and image data from memory. The second module is typically implemented in a low priority routine, such as a task level routine, to allow for the routine to be executed systematically in accordance with priority.

Abstract: An improved method and device for capturing image data benefits from having a single central processor execute the operating system, and the image capture, decode and processing programs. A method for capturing of image data comprises transmitting image data from an imager, assembling the image data, assigning a memory address to the assembled image data and transferring the assembled image data into system memory. This method is capable of central processing whereby the capturing of image data is executed via the main processor without having to invoke a dedicated processor or incorporate external components, such as additional PCBs, external digital signal processing or external data storage. Additionally, an imaging device comprises an image builder module that receives image data from the imager bus and assembles the data, and a transfer controller that initiates the image builder module and controls the transfer of image data into and out of memory.

Abstract: Data processing apparatus performs automatic hardware device identification and system setup in computer systems that have a Programmable Option Select (POS) feature, where the system includes multi-card adapters (adapters with attached daughter card(s)), and/or multi-card planar complexes (system boards with pluggable processor complexes and/or I/O risers). In particular, the apparatus uniquely identifies the aforementioned multi-card devices utilizing unique "combination type" POS IDs, where a combination type POS ID is a POS ID specifically preassigned to a combination of cards rather than to a single type of card. According to the invention, the unique combination type POS ID is partitioned across the combination of cards (for example, hardwired into each card). When the cards are combined, the partitioned ID is synthesized and becomes available to the system.