Patents by Inventor Jeffrey Demski
Jeffrey Demski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10361554Abstract: A circuit system includes a current sensor circuit, a subtractor circuit, a multiplier circuit, and a divider circuit. The current sensor circuit generates a current sense signal that indicates a current through an inductor. The circuit system generates a current value based on the current sense signal. The subtractor circuit determines a voltage difference across the inductor. The multiplier circuit multiplies the voltage difference by a time period that the voltage difference is applied across the inductor to generate a product. The divider circuit divides the product by the current value to generate an estimated inductance of the inductor.Type: GrantFiled: September 27, 2016Date of Patent: July 23, 2019Assignee: Altera CorporationInventors: Jeffrey Demski, Douglas Lopata, Ashraf Lotfi
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Patent number: 10020739Abstract: An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.Type: GrantFiled: March 27, 2014Date of Patent: July 10, 2018Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzalez
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Publication number: 20170331363Abstract: A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. A hysteretic comparison circuit compares the current in the power train circuit to positive and negative current limits. The hysteretic comparison circuit causes a positive current in the power train circuit to decrease in a positive current limit mode in response to the positive current in the power train circuit reaching the positive current limit. The hysteretic comparison circuit causes a negative current in the power train circuit to decrease in a negative current limit mode in response to the negative current in the power train circuit reaching the negative current limit. The hysteretic comparison circuit prevents a pulse width modulation controller from controlling the power train circuit during the positive and negative current limit modes.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Applicant: Altera CorporationInventors: Dominick Travaglini, Jeffrey Demski, Thomas Mathes, Sean Tarlton, Joseph Zbib
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Patent number: 9673192Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross member and a second cross member, and a first gain resistor including a first gain resistor metallic strip coupled to the first cross member. The semiconductor device also includes an amplifier over the substrate and coupled to the first gain resistor metallic strip.Type: GrantFiled: March 27, 2015Date of Patent: June 6, 2017Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9553081Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.Type: GrantFiled: November 27, 2013Date of Patent: January 24, 2017Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 9548714Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.Type: GrantFiled: December 29, 2008Date of Patent: January 17, 2017Assignee: Altera CorporationInventors: Ahmed Mohamed Abou-Alfotouh, Mirmira Ramarao Dwarakanath, Jeffrey Demski
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Patent number: 9536938Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.Type: GrantFiled: March 27, 2015Date of Patent: January 3, 2017Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9508785Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.Type: GrantFiled: March 27, 2015Date of Patent: November 29, 2016Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9443839Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.Type: GrantFiled: November 27, 2013Date of Patent: September 13, 2016Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 9299691Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.Type: GrantFiled: November 27, 2013Date of Patent: March 29, 2016Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20150280558Abstract: An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: ALTERA CORPORATIONInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzalez
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Publication number: 20140159130Abstract: An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device.Type: ApplicationFiled: November 27, 2013Publication date: June 12, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151794Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151795Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151797Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 8698463Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.Type: GrantFiled: December 29, 2008Date of Patent: April 15, 2014Assignee: Enpirion, Inc.Inventors: Mirmira Ramarao Dwarakanath, Jeffrey Demski, Ahmed Mohamed Abou-Alfotouh
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Publication number: 20120153912Abstract: A controller, power converter and method of controlling a power switch therein to improve power conversion efficiency at low output current. In one embodiment, the power converter includes a power switch coupled to a source of electrical power, and a controller coupled to a control terminal of the power switch and to an output of the power converter. The controller is configured to control a conductivity of the power switch at a selected switching frequency from a set of discrete switching frequencies as a function of an output characteristic of the power converter.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Inventors: Jeffrey Demski, Douglas Dean Lopata
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Publication number: 20100164650Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventors: Ahmed Mohamed Abou-Alfotouh, Mirmira Ramarao Dwarakanath, Jeffrey Demski
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Publication number: 20100164449Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventors: Mirmira Ramarao Dwarakanath, Jeffrey Demski, Ahmed Mohamed Abou-Alfotouh