Abstract: Over-sampled data is filtered by receiving a word of over-sampled data including sample bits for each of a plurality of data bits, detecting a sample bit having one logic value and, on either side of it, bits having the opposite logic value and, upon such detection, outputting the received word with the sample bit having the one logic value inverted.

Abstract: An improved memory controller of a computer system is described. The computer system includes a microprocessor and a memory coupled to the memory controller that controls access to the memory. An interface circuit is coupled to the microprocessor for receiving a first address to access the memory. The memory includes a first memory bank and a second memory bank. A memory control circuit is coupled to the interface circuit for generating control signals to access the memory. An address generation circuit is coupled to receive the first address from the interface circuit for generating a first memory address and a second memory address in accordance with the first address to access the memory during a burst access to the memory from the microprocessor.

Abstract: A memory controller for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller also allows access between the microprocessor and the plurality of devices. The memory controller interfaces the microprocessor and the plurality of devices. The memory controller comprises an interface circuit coupled to the microprocessor and the plurality of devices to receive an access request from one of the microprocessor and the plurality of devices for determining whether the access request is a memory access request for the memory array. A memory control circuit is coupled to the interface circuit for controlling access to the memory array when the access request is the memory access request.

Abstract: A clock generation and distribution system for a memory controller in a computer system is described. The memory controller includes a CPU interface circuit-that interfaces with a microprocessor, a bus controller interface circuit that interfaces with a bus controller, and a main memory controller circuit coupled to a memory for controlling memory operations of the memory. The clock generation and distribution system includes a clock generation circuit for generating a first clock signal in accordance with an input clock signal. A delay circuit delays the first clock signal to be a delayed first clock signal. The delay circuit has a controllable delay.