Patents by Inventor Jeffrey Fook

Jeffrey Fook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050127531
    Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.
    Type: Application
    Filed: January 24, 2005
    Publication date: June 16, 2005
    Inventors: Wuu Tay, Jeffrey Fook
  • Publication number: 20050023651
    Abstract: A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 3, 2005
    Inventors: Dalson Kim, Jeffrey Fook, Lee Kuan
  • Publication number: 20050023654
    Abstract: A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.
    Type: Application
    Filed: March 10, 2004
    Publication date: February 3, 2005
    Inventors: Dalson Seng Kim, Jeffrey Fook, Lee Kuan