Abstract: An improved capacitor is provided wherein the capacitor has an improved bond between the anode and anode wire. The anode comprises a pressed anode powder comprising a first density region and a second density region wherein the second density region has a higher density than the first density region. An anode wire extends into the second density region wherein the anode wire in the second density region is distorted by compression. This allows for better utilization of the metal powder surface area by allowing a lower bulk press density and lower sinter temperature while still achieving the necessary wire pull strength. In addition, this invention when utilized with deoxidation steps, results in sufficient wire pull strengths not possible otherwise.

Abstract: A cast net support apparatus including a mouthguard assembly and a cast net assembly is disclosed. These assemblies in conjunction with one another provide an easy-to-use casting net solution. The mouthguard assembly includes a mouthguard that is detachably tethered to the cast net assembly. The mouthguard includes a tether that is fastened to a rod. The rod is then inserted into a buoyant cast net support attachment that is in turn fastened to a net. When the user prepares the net for casting, they will grip the mouthguard that is tethered to the net edge in their mouth. Thereby affording them better support of the net before casting. The better support allows for a further and more accurate cast of the net. As the user casts the net the mouthguard tether detaches from the net leaving the user with the mouthguard in the user's mouth.

Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.

Abstract: A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

Abstract: A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

Abstract: A folding knife includes a handle, an axle coupled to a first end of the handle, and a blade rotatably coupled to the axle. The blade includes a working portion and a tang, the blade having an open position in which the working portion extends from the handle and a closed position in which the working portion is substantially received within the handle. The folding knife further includes a lock having a locked position in which the lock prevents rotation of the blade and an unlocked position in which the lock permits rotation of the blade. The knife further includes a spring arm in the handle and a safety coupled to the handle, the safety having a first position in which the safety deflects the spring arm into the path of the lock to maintain the lock in the locked position and a second position in which the safety permits the lock to move from the locked position to the unlocked position.

Abstract: A folding knife includes a handle, an axle coupled to a first end of the handle, and a blade rotatably coupled to the axle. The blade includes a working portion and a tang, the blade having an open position in which the working portion extends from the handle and a closed position in which the working portion is substantially received within the handle. The folding knife further includes a lock having a locked position in which the lock prevents rotation of the blade and an unlocked position in which the lock permits rotation of the blade. The knife further includes a spring arm in the handle and a safety coupled to the handle, the safety having a first position in which the safety deflects the spring arm into the path of the lock to maintain the lock in the locked position and a second position in which the safety permits the lock to move from the locked position to the unlocked position.

Abstract: A process is provided to stabilize and/or reactivate an olefin production catalyst system which comprises contacting an olefin production catalyst system, either before or after use, with an aromatic compound.

Abstract: A fixed blade knife, includes a handle, and a blade, coupled to the handle. The blade has a tang received within the handle. A plurality of lashing points defined by passages extending through both the handle and the tang are provided. The knife may be carried in a sheath with a knife sharpener removably coupled to the sheath.