Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M?2).

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).

Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.

Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.

Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M≧2).

Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.

Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.

Abstract: In accordance with an embodiment of the present invention, a system for returning data comprises a storage array operable to store data received from at least one data source, a bypass circuit communicatively coupled with the storage array and operable to simultaneously stage data received from the at least one data source and a read data storage controller communicatively coupled with the storage array and the bypass circuit and operable to select a data return path of minimum latency from a plurality of data return paths for returning data selected from one of the storage array and the bypass circuit, based at least in part on at least one tag associated with each of the at least one data source, to a requesting device.

Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.

Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.

Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.

Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

Abstract: A composite transversely plastic interconnect for a microcarrier produces a carrier-to-substrate bond having low electrical resistance and high mechanical strength, significant bond height to mediate TCE mismatch between dissimilar carrier and substrate materials, and sufficient gap between the carrier and the substrate to permit effective post solder cleaning of the interconnect. A contact array consisting of solder balls is placed directly onto either of a carrier or a substrate interconnect surface with a stencil positioned to the chosen interconnect surface. The solder balls may have a selected melting temperature. Additionally, the solder balls may have a metallic coating, such as nickel or copper, or molten solder. The carrier and substrate are joined by mating an interconnect surface of each and applying heat. Solder paste may be applied to one of the interconnect surfaces to add additional height to the joint and compensate for lack of coplanarity between the carrier and the substrate.

Abstract: A composite transversely plastic interconnect for a microcarrier produces a carrier-to-substrate bond having low electrical resistance and high mechanical strength, significant bond height to mediate TCE mismatch between dissimilar carrier and substrate materials, and sufficient gap between the carrier and the substrate to permit effective post solder cleaning of the interconnect. A contact array consisting of solder balls is placed directly onto either of a carrier or a substrate interconnect surface with a stencil positioned to the chosen interconnect surface. The solder balls may have a selected melting temperature. Additionally, the solder balls may have a metallic coating, such as nickel or copper, or molten solder. The carrier and substrate are joined by mating an interconnect surface of each and applying heat. Solder paste may be applied to one of the interconnect surfaces to add additional height to the joint and compensate for lack of coplanarity between the carrier and the substrate.