Patents by Inventor Jeffrey G Holloway

Jeffrey G Holloway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8232144
    Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: July 31, 2012
    Assignee: Texas Instuments Incorporated
    Inventors: Bernhard P Lange, Anthony L Coyle, Jeffrey G Holloway
  • Publication number: 20100171201
    Abstract: Embodiments of a semiconductor device and method provide a quad flat no-lead semiconductor package which can have an arrangement of both chip-on-lead (COL) style leads and a die pad for supporting a die, and can also provide non-COL leads, both COL leads and a leadframe power pad, COL leads which have varying lengths to reduce stress resulting from thermal mismatch between a semiconductor die and leads, and a die pad with a curved, meandering edge to reduce stress resulting from thermal mismatch between the semiconductor die and the die pad.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Inventors: M. Todd Wyant, Jeffrey G. Holloway, Anthony L. Coyle
  • Publication number: 20070296056
    Abstract: An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance of the wire; the inductance is selected to fine-tune the high frequency characteristics of the circuit.
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anthony L. Coyle, Reynaldo C. Javier, Jeffrey G. Holloway
  • Publication number: 20070273010
    Abstract: The semiconductor device whose structure is formed from a die attached to a leadframe comprises a die having an attachment member, and a leadframe having a recess configured to receive a corresponding attachment member so as to establish a connection between the die and the leadframe.
    Type: Application
    Filed: May 29, 2007
    Publication date: November 29, 2007
    Applicants: TEXAS INSTRUMENTS INCORPORATED, TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Jeffrey G. Holloway, Steven A. Kummerl, Bernhard P. Lange