Abstract: Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

Abstract: Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples.

Abstract: Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output.

Abstract: In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset. The timing error is measured by the system and might be automatically adjusted by the appropriate amount in order to reduce or to eliminate the differential head error when a write event (as opposed to a read event) is activated.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples.

Abstract: In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.

Abstract: In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.

Abstract: Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit.

Abstract: In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset.

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: An offset history table is implemented and maintained in a BLUETOOTH device and is used to pre-seed an expected frequency offset of a received signal from another BLUETOOTH device. The disclosed offset history table includes one entry for each piconet device in a particular piconet, each entry including a best guess of the relevant piconet device's frequency offset with respect to the receiving BLUETOOTH device. Using a frequency offset history table and a pre-seeded frequency offset corresponding to an expected frequency offset based on the offset value maintained in the frequency offset history table, the performance of a BLUETOOTH device can be increased in a steady state piconet scenario.

Abstract: A method and apparatus for converting a full-rate digital clock circuit to a fractional-rate clock circuit. The combinatorial and sequential functions of the full rate design are duplicated, with a first combinatorial function responsive to even input logic vectors and a second combinatorial function responsive to odd input logic vectors. Output vectors from the first and the second combinatorial function are provided as input vectors to the respective first and second sequential function, which operate at a fractional clock rate and provide the output block vectors.