Abstract: Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify at least one of the plurality of cells as having performance margin. The speed-push mask is altered such that the at least one of the plurality of cells having performance margin may be fabricated as a non-speed-pushed cell. Additionally, a method for creating a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to identify at least one of the plurality of cells below a performance threshold. A speed-push mask is created such that the at least one of the plurality of cells below the performance threshold may be fabricated as a speed-pushed cell.

Abstract: An applicator includes a hollow body having a central longitudinal axis to hold a colored ink, a shoulder portion, a central recessed portion, and a base portion. The shoulder portion is located above and merges with the central recessed portion at an upper end thereof and includes a top wall having an opening. The base portion is located below and merges with the central recessed portion at a lower end thereof and includes a bottom wall. The central recessed portion has a smooth continuous sidewall formed as a triangle with three sides of substantially identical dimensions. The central recessed portion merges with the shoulder portion and the base portion at upper and lower flared surfaces, respectively.

Abstract: A system and method of scheduling RFID tag interrogations by a plurality of RFID readers so as to mitigate the effects of interference within an RFID environment in which the readers are deployed, and to enhance the efficiency and reliability of the overall RFID system. The system includes a plurality of RFID receivers for receiving RFID tag data, a plurality of RFID tag interrogators for transmitting RF interrogation signals for interrogating RFID tags, and a controller for providing to at least one interrogator, at least one receiver, and at least one tag, a parameter associated with operational characteristics of the interrogator, the receiver, and the tag, respectively. The interrogator, the receiver, and the tag are operative, in response to receipt of the respective parameter, to modify its operational characteristics in accordance with the respective parameter, thereby avoiding interference at the receivers and the tags.

Abstract: A system and method for monitoring and characterizing various sources of RF interference within an RFID environment, and for adjusting the operational characteristics of an array of RFID readers within the system based on these interference characterizations. The system examines the received transmissions from readers in the network by controlling a calibration cycle or while they are operating as interrogators to determine interference parameters, and to verify the operation of the readers in the array. The system also examines outside sources of interference, and signal dependent interference. The interference characterization can also be estimated from a combination of calculations and co-monitoring.

Abstract: A system and method of determining locations of one or more RFID tags within an RFID environment. The system includes a plurality of RFID readers, each operative to transmit and receive RF signals for scanning a tag disposed within an RF coverage region associated with the reader, and for receiving tag data in response to the scanning of the tag. A plurality of sub-locations is determined within the environment, each corresponding to at least a portion of at least one of a plurality of RF coverage regions associated with the readers. The sub-locations are mapped to a plurality of predefined locations within the environment. A reader scans a tag, and receives tag scan data from the tag in response to the scanning of the tag. The tag scan data includes a tag identifier associated with the scanned tag. The tag scan data is mapped to the sub-locations based on the RF coverage region associated with the reader.

Abstract: An architecture of an RFID system that facilitates the accessing of RFID tag data within an RFID environment. The architecture includes a plurality of RFID readers, each reader being operative to transmit a first RF signal for scanning at least one RFID tag disposed within an RF coverage region associated with the reader, and to receive at least one second RF signal including tag data in response to the scanning of the tag. The architecture further includes at least one host computer operative to execute at least one client application, and at least one controller/processor communicably coupled to the plurality of readers and the at least one host computer. The controller/processor is operative to control operation of the plurality of readers, to process the tag data received by the plurality of readers, and to provide the processed tag data to the at least one host computer for use by the at least one client application executing thereon.

Abstract: A system and method that facilitates the configuration and control of components of a radio frequency identification (RFID) system, taking into account how the RFID system components are associated with one or more physical locations within an environment in which the RFID system is deployed. The RFID system can be controlled by obtaining a representation of the physical space. Next, at least one region of interest is specified in the representation of the physical space. An interrogation zone is then specified in the representation of the physical space, in which the interrogation zone corresponds to the data reader. Next, at least one overlap region of the interrogation zone and the region of interest is specified. Information is then stored, including the representation, and the interest region, the interrogation zone, and/or the overlap region. Operation of the data reader is controlled as a function of the stored information.

Abstract: A system and method that facilitates the configuration and control of components of an RFID system, taking into account how the RFID system components are associated with one or more physical locations within an environment in which the RFID system is deployed. A user provides information specifying associations between the system components and the physical locations within the environment to obtain visual representations of configuration data generated therefrom with reference to a facility view, an RF coverage view, and a location view of the data. The facility view serves as a reference plane for placement and orientation of antennas associated with RFID readers, location benchmark tags, and the physical locations of interest. After each antenna is placed and oriented on the facility view, an estimate of the size and shape of the RF interrogation zone of each antenna is computed, and representations of the RF interrogation zones are provided on the facility view to obtain the RF coverage view of the data.

Abstract: An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.

Abstract: A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.

Abstract: An apparatus and method for communicating data between at least two data devices, suitable for use as a wireless local-area network, that provides robust data communication via a radio communications channel corrupted by multipath interference, particularly at high data rates. A preferred embodiment of the invention represents data as a sequence of Walsh-function waveforms encoded by pseudo-noise direct-sequence spread-spectrum modulation. Walsh-function-encoding of the data provides a long symbol duration, thereby allowing the spread-spectrum modulation to provide processing gain sufficient to substantially overcome multipath interference, while providing a high data rate. In another preferred embodiment, Walsh-function modulation is supplemented with various forms of phase modulation, such as coherent PSK for bi-orthogonal signalling, and DPSK between orthogonal symbols for noncoherent bi-orthogonal signalling, thereby further increasing data rate without reducing processing gain.

Abstract: An apparatus and method for communicating data between at least two data devices, suitable for use as a wireless local-area network, that provides robust data communication via a radio communications channel corrupted by multipath interference, particularly at high data rates. A preferred embodiment of the invention represents data as a sequence of Walsh-function waveforms encoded by pseudo-noise direct-sequence spread-spectrum modulation. Walsh-function-encoding of the data provides a long symbol duration, thereby allowing the spread-spectrum modulation to provide processing gain sufficient to substantially overcome multipath interference, while providing a high data rate. In another preferred embodiment, Walsh-function modulation is supplemented with various forms of phase modulation, such as coherent PSK for bi-orthogonal signalling, and DPSK between orthogonal symbols for noncoherent bi-orthogonal signalling, thereby further increasing data rate without reducing processing gain.

Abstract: A data communications system for conveying a series of input data symbols includes a transmitter subsystem and a receiver subsystem. The transmitter subsystem generates a series of composite waveforms corresponding to a series of input data symbols by selecting from a set of mutually orthogonal component waveforms, then combines contemporaneous portions of at least two of the component waveforms so as to form a composite waveform which is unique to the data symbol. The transmit subsystem uses the composite waveform to modulate a carrier signal and transmits the carrier signal over a communications channel. The receiver subsystem receives the carrier signal and recovers the composite waveform from the carrier signal. The receiver subsystem identifies the data symbol by, at least in part, decompositioning the composite waveforms into their constituent component waveforms so as to identify which composite waveforms have been transmitted.

Abstract: An apparatus and method for communicating data between at least two data devices, suitable for use as a wireless local-area network, that provides robust data communication via a radio communications channel corrupted by multipath interference, particularly at high data rates. A preferred embodiment of the invention represents data as a sequence of Walsh-function waveforms encoded by pseudo-noise direct-sequence spread-spectrum modulation. Walsh-function-encoding of the data provides a long symbol duration, thereby allowing the spread-spectrum modulation to provide processing gain sufficient to substantially overcome multipath interference, while providing a high data rate. In another preferred embodiment, Walsh-function modulation is supplemented with various forms of phase modulation, such as coherent PSK for bi-orthogonal signalling, and DPSK between orthogonal symbols for noncoherent bi-orthogonal signalling, thereby further increasing data rate without reducing processing gain.

Abstract: A hydroacoustic communication system employs spread spectrum to mitigate multipath interference caused by acoustic reflections off underwater surfaces and other large boundaries or acoustic discontinuities. The system is particularly beneficial for mitigating errors due to surface reflections, and for mitigating interference due to unwanted signals having a delay ranging from tens of microseconds to hundreds of milliseconds.