Abstract: A system is disclosed for charging (recharging) and discharging a battery pack comprising a plurality of battery cells. The system may execute an iterative process of monitoring a frequency corresponding to the minimum impedance value of the battery pack or cell(s) of the pack and adjusting the charge energy signals applied to the battery pack. In some instances, taps may be provided within the battery pack to monitor the frequency response to the charge energy signal for one or more cells of the battery pack. In other instances, the battery pack as a unit may be monitored iteratively. This process may maintain a relative charge balance across the cells of the battery pack, decrease the time to recharge the battery pack, extend the life of the pack, optimize the amount of current charging the battery pack, and avoid energy lost to various inefficiencies.

Abstract: Systems and methods that charge a battery using a signal with at least one harmonically tuned aspect based on impedance of the battery with a frequency or harmonic component. The system may further involve a power converter that may act in concert with charging to power a load. In some instances, an output signal is generated that is interleaved with the charge signal. Further, the output signal may be tuned based on output impedance to the discharge signal.

Abstract: A system is disclosed for determining complex impedance characteristics of one or more battery cells based on the charge signal applied, or to be applied, to the battery cell. Implementations may include measuring the impedance of a battery cell to, in some instances, determine a frequency component or harmonic that defines, at least a portion, of a waveform shape for charging the battery cell. In one implementation, the impedance at the battery cell may be measured or estimated from a discrete charge period being applied to the battery cell or from multiple discrete charge periods applied to the battery cell. The measured differences between the amplitude and time components of the voltage and current waveforms may be used to determine or estimate the magnitude, phase shift, real, and/or imaginary values of the impedance at the battery cell.

Abstract: Methods and systems for charging (recharging) one or more battery cells are presented by generating a harmonically tuned charge signal, which may involve pulses of a charge signal. The harmonically tuned charge signal includes or otherwise corresponds to a harmonic frequency or frequencies associated with an optimal transfer of energy based on a real and/or an imaginary value of the energy transfer of the battery cell. In one example, the harmonic frequency or frequencies, sometimes generally referred to as harmonics, may be associated with a minimum real impedance value of the battery cell. Aspects involve optimizing a charge signal corresponding to a harmonic, or harmonics, associated with minimum real or resistance and/or minimum imaginary or reactance impedance values of a battery cell. Such a charge signal may improve the efficiency when charging the battery cell by reducing lost energy due to high impedance at the electrodes of the battery cell.

Abstract: An improved device, of the type utilizing a display having pixels identified by a two-axis coordinate system, displays line segments referenced to the same coordinate system under control of a digital computer. The coordinate system, for example, having standard rectangular X and Y Cartesian coordinates, is configured so that each pixel lies at the intersection of a coordinate line from each of the axes. The improvement has an arrangement for determining as a major axis the axis of the coordinate system with respect to which the line moves most, and for defining the other one of the axes as the minor axis. For each major axis coordinate line crossing of the line segment, a pixel selection arrangement selects for display a pixel that both lies on the major axis coordinate line and has a minor axis coordinate that is closest to the line segment.

Abstract: A system and method for controlling a slave processor from a master processor in which the slave processor is instructed to await the occurrence of a particular event and the arrival of a number of data words before processing additional requests. A wait request from the master processor includes identification of an event which must occur before processing is to resume. The master processor provides a number to a register accessible to the slave processor to indicate how many data words to await. The slave processor discontinues processing upon receiving the wait request. The slave processor detects the occurrence of the event and the arrival of the data words and then resumes processing. The register may include an indicator or flag that indicates when the number of data words set by the master processor has been received.

Abstract: A 3D graphics processing system in a preferred embodiment has an input for a digital video data stream. The system has a graphics engine, for processing graphics request code and data, in communication with a host computer over a data bus and also in communication with a frame buffer. It also has an input for a digital video data stream, and the input is in communication with the graphics engine. A control arrangement interrupts processing by the graphics engine of conventional graphics request code and data to permit priority processing of the digital video data stream. In this manner, an image associated with the digital video data stream may be displayed in real time in a desired plane that may be accessed and processed by the graphics processing system as a graphic image.

Abstract: A device is provided for managing vertex lists. In particular, in one embodiment, the device permits management of the communication, in a digital computing system having a graphics processor, of a sequence of data records associated with successive vertices. The vertex data are typically used for drawing polyline figures or triangular mesh, or other figures using coordinates. Each record includes at least one floating point value that provides at least a first datum associated with a vertex. The device comprises an arrangement for placing the sequence of data records in a data stream, as well as an arrangmement for placing at the end of the data stream a data record in which the floating point value providing the first datum is set to a value corresponding to Not a Number. In this manner it can be established when the sequence of records is complete without the need for any extra control bits. Related methods are also provided.

Abstract: An improved graphics processor is of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine. The buffer is also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine. The improvement in a preferred embodiment utilizes a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer. User access via an application is provided only to the normal FIFO, whereas system level code is provided access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor. In a further embodiment, a logical sync FIFO is employed also. The sync FIFO is used in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing. Related methods are also provided.