Abstract: An electronics circuit for digitizing an analog audio or like data signal to a six bit digital equivalent signal and then introducing a dither component into the digital equivalent signal. The electronics circuit includes an Erasable Programmed Read Only Memory (EPROM) which generates a six bit dither component to be added to the digital equivalent signal. A binary adder adds a dither bit to each of the six bits of the digital equivalent signal and then provides a three bit equivalent digital signal. The three bit equivalent digital signal is then written in parallel into a first storage register, while one bit of the three bit digital equivalent signal is written into a second storage register. When a fuze active signal, which is input to the present invention, is a logic zero the first register is enabled for a read operation allowing the three bit equivalent digital data to be read from the first register to a parallel to serial converter which converts the data to a serial three bit digital format.

Abstract: A digital interface for allowing a first device which receives and sends information serially to communicate with a second device which receives and sends information in parallel. The first device may be an encryption unit while the second device may be a relay/responder/reporter connected to a transmitter or a digital signal processing unit. The digital interface comprises an erasable programmable logic device which during an uplink data transfer performs the function of converting parallel logic signals, that is control signals and data words provided by the relay/responder/reporter, for example, to commands and data to be transmitted by a transmitter serially to the encryption unit. In a like manner, the erasable programmable memory device during a downlink data transfer converts serial commands and data received from the encryption unit by a receiver to a parallel format for transmission to the relay/responder/reporter.