Patents by Inventor Jeffrey Jude Loescher

Jeffrey Jude Loescher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10318685
    Abstract: A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Mark William Bales, David L. Peart, Jeffrey Jude Loescher
  • Patent number: 9697313
    Abstract: In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 4, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Mark William Bales, Jeffrey Jude Loescher, Paul Furnanz
  • Publication number: 20160267204
    Abstract: A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.
    Type: Application
    Filed: September 21, 2015
    Publication date: September 15, 2016
    Inventors: Mark William Bales, David L. Peart, Jeffrey Jude Loescher