Patents by Inventor Jeffrey Koon Yee Lee
Jeffrey Koon Yee Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734048Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.Type: GrantFiled: June 5, 2018Date of Patent: August 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
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Patent number: 10679718Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.Type: GrantFiled: October 4, 2017Date of Patent: June 9, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mai Ghaly, Chandan Mishra, Amir Hossein Gholamipour, Yuheng Zhang, Jeffrey Koon Yee Lee, James Hart, Daniel Helmick
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Publication number: 20190371380Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Inventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
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Publication number: 20190103168Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.Type: ApplicationFiled: October 4, 2017Publication date: April 4, 2019Applicant: Western Digital Technologies, Inc.Inventors: MAI GHALY, CHANDAN MISHRA, AMIR HOSSEIN GHOLAMIPOUR, YUHENG ZHANG, JEFFREY KOON YEE LEE, JAMES HART, DANIEL HELMICK
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Patent number: 9595325Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.Type: GrantFiled: March 31, 2016Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Chang Siau, Jeffrey Koon Yee Lee, Tianhong Yan, Yingchang Chen, Gopinath Balakrishnan, Tz-yi Liu
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Publication number: 20160217854Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Applicant: SanDisk Technologies Inc.Inventors: Chang Siau, Jeffrey Koon Yee Lee, Tianhong Yan, Yingchang Chen, Gopinath Balakrishnan, Tz-yi Liu
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Patent number: 9318194Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.Type: GrantFiled: September 29, 2014Date of Patent: April 19, 2016Assignee: SanDisk 3D LLCInventors: Chang Siau, Jeffrey Koon Yee Lee, Tianhong Yan, Yingchang Chen, Gopinath Balakrishnan, Tz-yi Liu
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Publication number: 20160093373Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Chang Siau, Jeffrey Koon Yee Lee, Tianhong Yan, Yingchang Chen, Gopinath Balakrishnan, Tz-yi Liu
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Patent number: 8885428Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.Type: GrantFiled: February 22, 2013Date of Patent: November 11, 2014Assignee: Sandisk 3D LLCInventors: Yingchang Chen, Jeffrey Koon Yee Lee
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Publication number: 20140241090Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: SANDISK 3D LLCInventors: Yingchang Chen, Jeffrey Koon Yee Lee
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Patent number: 8374051Abstract: A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed.Type: GrantFiled: March 3, 2011Date of Patent: February 12, 2013Assignee: SanDisk 3D LLCInventors: Tianhong Yan, Gopinath Balakrishnan, Jeffrey Koon Yee Lee, Tz-yi Liu
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Publication number: 20120224408Abstract: A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Inventors: Tianhong Yan, Gopinath Balakrishnan, Jeffrey Koon Yee Lee, Tz-yi Liu
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Patent number: 8223525Abstract: A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array.Type: GrantFiled: December 15, 2009Date of Patent: July 17, 2012Assignee: SanDisk 3D LLCInventors: Gopinath Balakrishnan, Jeffrey Koon Yee Lee, Yuheng Zhang, Tz-Yi Liu, Luca Fasoli
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Patent number: 8111539Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.Type: GrantFiled: December 19, 2008Date of Patent: February 7, 2012Assignee: SanDisk 3D LLCInventors: Luca G. Fasoli, Tianhong Yan, Jeffrey Koon Yee Lee
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Publication number: 20110141788Abstract: A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Inventors: Gopinath Balakrishnan, Jeffrey Koon Yee Lee, Yuheng Zhang, Tz-Yi Liu, Luca Fasoli
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Publication number: 20090323392Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.Type: ApplicationFiled: December 19, 2008Publication date: December 31, 2009Inventors: Luca G. Fasoli, Tianhong Yan, Jeffrey Koon Yee Lee