Abstract: A configurable video sequence viewing and recording system stores multiple computer generated images of a sequence in a frame buffer and plays back the images for animation motion study. The images are stored either in a full size format or in a decimated format according to a decimation factor. The images are read out in real time for display from the frame buffer, with pixels/lines/frames being replicated to provide full size images for a desired number of frames each. The number of images of a sequence to be displayed/stored are determined by an operator, and a loop function is provided so that the sequence may be continuously displayed.

Abstract: A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.

Abstract: An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus.