Patents by Inventor Jeffrey L. Blouse

Jeffrey L. Blouse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5266504
    Abstract: A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: November 30, 1993
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey L. Blouse, Jack O. Chu, Brian Cunningham, Jeffrey P. Gambino, Louis L. Hsu, David E. Kotecki, Seshadri Subbanna, Zu-Jean Tien
  • Patent number: 5132765
    Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: July 21, 1992
    Inventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg
  • Patent number: 5008207
    Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: April 16, 1991
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg