Patents by Inventor Jeffrey M. Solomon
Jeffrey M. Solomon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240166557Abstract: Described herein is coated article comprising: (a) a substrate comprising a ceramic, a glass, or a glass ceramic, wherein the substrate comprises a surface, the surface comprising a continuous upper portion and a plurality of lower portions, wherein each lower portion is connected to the upper portion by at least one sidewall; and (b) a first layer comprising a material capable of physical vapor deposition, wherein the first layer is disposed on the continuous upper portion and at least a portion of each sidewall and wherein at least a portion of each lower portion is free of the first layer. Methods of making such coated articles are described herein, wherein the substrate is coating via angular physical vapor deposition.Type: ApplicationFiled: April 4, 2022Publication date: May 23, 2024Inventors: Joshua M. Fishman, Paul B. Armstrong, Amir Gharachorlou, Kathleen M. Humpal, Melissa A. Lackey, Christopher S. Lyons, Mark J. Pellerite, James A. Phipps, Jeffrey L. Solomon, Karl K. Stensvad, Tarris A. Sveback, Brylee David B. Tiu
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Publication number: 20240151646Abstract: Luminescent imaging films (100) for fluorescent enhancement and methods of making and using the same are provided. The films (100) include a flexible carrier layer (1109, and a pattern of photonic structure (120) disposed on the flexible carrier layer, which is interspersed with an anti-biofouling material (130) to provide a pattern of analyte sites (132). The pattern of photonic structure includes a patterned high-refractive-index dielectric material surface (123) so as to provide resonance at the excitation or emission wavelength to enhance a fluorescence signal from labeled analytes.Type: ApplicationFiled: April 7, 2022Publication date: May 9, 2024Inventors: Xuexue Guo, Henrik B. van Lengerich, Joshua M. Fishman, Karl K. Stensvad, Cedric Bedoya, Caleb T. Nelson, Kayla C. Niccum, John A. Wheatley, Jeffrey L. Solomon, Johah Shaver
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Patent number: 8651862Abstract: A dental tool may include a head that may include a working portion and a neck. The neck may include a first end and a second end, and the working portion may extend from the first end. A handle may include a clamp and a socket. The socket may be configured to receive the second end of the neck. The second end may pivot within the socket to move the working portion and the neck relative to the handle. The clamp may be adapted to selectively fix the second end relative to the handle.Type: GrantFiled: February 15, 2012Date of Patent: February 18, 2014Inventor: Jeffrey M. Solomon
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Publication number: 20120244486Abstract: A dental tool may include a head that may include a working portion and a neck. The neck may include a first end and a second end, and the working portion may extend from the first end. A handle may include a clamp and a socket. The socket may be configured to receive the second end of the neck. The second end may pivot within the socket to move the working portion and the neck relative to the handle. The clamp is may be adapted to selectively fix the second end relative to the handle.Type: ApplicationFiled: February 15, 2012Publication date: September 27, 2012Inventor: Jeffrey M. SOLOMON
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Patent number: 6886148Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: GrantFiled: December 10, 2002Date of Patent: April 26, 2005Assignee: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
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Publication number: 20030076722Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: ApplicationFiled: December 10, 2002Publication date: April 24, 2003Applicant: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
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Patent number: 6493858Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: GrantFiled: July 10, 2001Date of Patent: December 10, 2002Assignee: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
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Publication number: 20020162081Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: ApplicationFiled: July 10, 2001Publication date: October 31, 2002Applicant: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
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Patent number: 5185638Abstract: The illumination system as a part of an optical inspection system, the total inspection system itself, and the method of illuminating and inspecting a workpiece. The illumination system is computer controlled as to a level of intensity and adjustable as to angle of incidence. The illumination system includes illumination control electronics, a quad quartz halogen lamp array light source, a fiber optic line converter and an illumination collection system, having a collimator lens array and a focusing/field coverage lens. As a result of the present invention, determinations of false defects on the PCB are minimized. Human contact with the PCB is also minimized and the rate of inspections performable is increased.Type: GrantFiled: April 26, 1991Date of Patent: February 9, 1993Assignee: International Business Machines CorporationInventors: Vincent C. Conzola, Norman E. Rittenhouse, Jeffrey M. Solomon, Thomas J. Toomey, Peter J. Yablonsky