Patents by Inventor Jeffrey M. Solomon
Jeffrey M. Solomon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240318613Abstract: A gas turbine engine is provided. The gas turbine engine includes a turbomachine defining an engine inlet to an inlet duct, a fan duct inlet to a fan duct, and a core inlet to a core duct; a primary fan driven by the turbomachine; and a secondary fan located downstream of the primary fan within the inlet duct. The gas turbine engine defines a thrust to power airflow ratio between 3.5 and 100 and a core bypass ratio between 0.1 and 10, wherein the thrust to power airflow ratio is a ratio of an airflow through a bypass passage over the turbomachine plus an airflow through the fan duct to an airflow through the core duct, and wherein the core bypass ratio is a ratio of the airflow through the fan duct to the airflow through the core duct.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Inventors: Brandon Wayne Miller, Randy M. Vondrell, David Marion Ostdiek, Craig Williams Higgins, Alexander Kimberley Simpson, Syed Arif Khalid, Jeffrey S. Spruill, Daniel Lawrence Tweedt, William Joseph Solomon, Kevin Edward Hinderliter
-
Patent number: 12097498Abstract: An article includes a flexible structured film with a first major surface and a second major surface, wherein a first major surface of the flexible structured film has a plurality of posts separated by land areas, and the posts have an exposed surface. An anti-biofouling layer resides in the land areas, and the anti-biofouling layer has a methylated surface. An inorganic layer is on the exposed surfaces of the posts, wherein the inorganic layer includes a metal or a metal oxide. An analyte binding layer is on the inorganic layer, wherein the analyte binding layer is chosen from a reactive silane, a functionalizable hydrogel, a functionalizable polymer, and mixtures and combinations thereof. An exposed surface of the analyte binding layer includes at least one functional group selected to bind with a biochemical analyte.Type: GrantFiled: November 24, 2021Date of Patent: September 24, 2024Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Henrik B. van Lengerich, Caleb T. Nelson, Kayla C. Niccum, Jeffrey L. Solomon, Paul B. Armstrong, Joshua M. Fishman, Tonya D. Bonilla, Phillip D. Hustad, David J. Tarnowski
-
Patent number: 8651862Abstract: A dental tool may include a head that may include a working portion and a neck. The neck may include a first end and a second end, and the working portion may extend from the first end. A handle may include a clamp and a socket. The socket may be configured to receive the second end of the neck. The second end may pivot within the socket to move the working portion and the neck relative to the handle. The clamp may be adapted to selectively fix the second end relative to the handle.Type: GrantFiled: February 15, 2012Date of Patent: February 18, 2014Inventor: Jeffrey M. Solomon
-
Publication number: 20120244486Abstract: A dental tool may include a head that may include a working portion and a neck. The neck may include a first end and a second end, and the working portion may extend from the first end. A handle may include a clamp and a socket. The socket may be configured to receive the second end of the neck. The second end may pivot within the socket to move the working portion and the neck relative to the handle. The clamp is may be adapted to selectively fix the second end relative to the handle.Type: ApplicationFiled: February 15, 2012Publication date: September 27, 2012Inventor: Jeffrey M. SOLOMON
-
Patent number: 6886148Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: GrantFiled: December 10, 2002Date of Patent: April 26, 2005Assignee: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
-
Publication number: 20030076722Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: ApplicationFiled: December 10, 2002Publication date: April 24, 2003Applicant: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
-
Patent number: 6493858Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: GrantFiled: July 10, 2001Date of Patent: December 10, 2002Assignee: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
-
Publication number: 20020162081Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.Type: ApplicationFiled: July 10, 2001Publication date: October 31, 2002Applicant: The Board of Trustees of the Leland Stanford Jr. UniversityInventor: Jeffrey M. Solomon
-
Patent number: 5185638Abstract: The illumination system as a part of an optical inspection system, the total inspection system itself, and the method of illuminating and inspecting a workpiece. The illumination system is computer controlled as to a level of intensity and adjustable as to angle of incidence. The illumination system includes illumination control electronics, a quad quartz halogen lamp array light source, a fiber optic line converter and an illumination collection system, having a collimator lens array and a focusing/field coverage lens. As a result of the present invention, determinations of false defects on the PCB are minimized. Human contact with the PCB is also minimized and the rate of inspections performable is increased.Type: GrantFiled: April 26, 1991Date of Patent: February 9, 1993Assignee: International Business Machines CorporationInventors: Vincent C. Conzola, Norman E. Rittenhouse, Jeffrey M. Solomon, Thomas J. Toomey, Peter J. Yablonsky