Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: A phase detector for a multi-channel PSK receiver is provided with a plurality of phase channels. Each of the phase channels has its own comparator coupled to an electronic switch for producing signals which are the products of the analog data inputs on the phase channels. The outputs from the electronic switches are connected to positive and negative summing circuits and the output of the positive and negative summing circuits are connected to the positive and negative inputs of a differential amplifier which produce a sum of the difference of the absolute value of the analog data inputs which is employed as an error voltage signal to control the frequency of a voltage controlled oscillator in a multi-channel PSK receiver. By eliminating convention analog multipliers in the phase detector, the phase detector is capable of generating error voltage signals from analog data input signals having data rates as high as 5 gigabytes per second.