Patents by Inventor Jeffrey MARKHAM

Jeffrey MARKHAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10936593
    Abstract: In a method for resolving a query to a database, a server computing system receives a query for retrieving objects from a client device. A candidate data set of objects is determined by applying the query to the database, the candidate data set of objects including identifiers of objects satisfying the query. The candidate data set of objects is transmitted to the client computing device as the identifiers. A request for a subset of the objects corresponding to identifiers of the candidate data set of objects from the server computing system for identifiers of the candidate data set of objects that do not match the identifiers of objects stored in the cache of the client computing device is received. The subset of objects is transmitted to the client device.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: March 2, 2021
    Assignee: Liberation Distribution, Inc.
    Inventors: Cheryl Murphy Durzy, Richard Brashears, David Cross, Jeffrey Markham
  • Patent number: 10296695
    Abstract: Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Publication number: 20180276729
    Abstract: In a method for providing business to business alcohol product distribution, a distributor maintains a virtual inventory of alcohol products at a computing system, where the virtual inventory is populated by suppliers of the alcohol products. Access to the virtual inventory of alcohol products to is provided to resellers, where the alcohol products accessible to the resellers for purchase are based at least in part on sales markets and license types of the respective resellers. Responsive to a purchase request from a reseller for a particular alcohol product, a purchase of the particular alcohol product by the distributor from a supplier of the particular alcohol product is effectuated. Transport of the particular alcohol product from the supplier to the reseller is effectuated. Legal possession of the particular alcohol product is transferred from the distributor to the reseller.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 27, 2018
    Applicant: Liberation Distribution, Inc.
    Inventors: Cheryl Murphy DURZY, Richard BRASHEARS, David CROSS, Jeffrey MARKHAM
  • Publication number: 20180276217
    Abstract: In a method for resolving a query to a database, a server computing system receives a query for retrieving objects from a client device. A candidate data set of objects is determined by applying the query to the database, the candidate data set of objects including identifiers of objects satisfying the query. The candidate data set of objects is transmitted to the client computing device as the identifiers. A request for a subset of the objects corresponding to identifiers of the candidate data set of objects from the server computing system for identifiers of the candidate data set of objects that do not match the identifiers of objects stored in the cache of the client computing device is received. The subset of objects is transmitted to the client device.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 27, 2018
    Applicant: Liberation Distribution, Inc.
    Inventors: Cheryl Murphy DURZY, Richard BRASHEARS, David CROSS, Jeffrey MARKHAM
  • Patent number: 10049175
    Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 14, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Min Cao, Roland Ruehl, Jeffrey Markham
  • Patent number: 9563737
    Abstract: Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 7, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alexandre Arkhipov, Jeffrey Markham, Karun Sharma
  • Patent number: 9396301
    Abstract: Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 9372955
    Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 21, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 9164969
    Abstract: Disclosed is a method, system, and computer program product for implementing efficient access to stream data. The present approach implements a stream reader that supports either reading the entire layout (e.g., loading the contents of the user-specified top cell and all its progeny) into memory, or just a portion of it (e.g., loading only the contents of the user-specified top cell and its progeny that overlapped a user-specified bounding box). Some approaches provide a mechanism to implement parallelized or multithreaded reads of the stream data.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 20, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Udayan Anand Gumaste, Roland Ruehl, Jeffrey Markham
  • Patent number: 9117052
    Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 25, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey Salowe, Min Cao, Roland Ruehl, Jeffrey Markham
  • Patent number: 8806405
    Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Regis Colwell, Arnold Ginetti, Khalid ElGalaind, Thomas Jordan, Jose A. Martinez, Jeffrey Markham, Steven Riley, Chung-Do Yang
  • Patent number: 8719765
    Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Min Cao, Jeffrey Markham
  • Publication number: 20140123094
    Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Regis Colwell, Arnold Ginetti, Khalid ElGalaind, Thomas Jordan, Jose A. Martinez, Jeffrey Markham, Steven Riley, Chung-Do Yang
  • Patent number: 8645902
    Abstract: Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: February 4, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Jeffrey Markham, Min Cao, Roland Ruehl
  • Patent number: 8429574
    Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: April 23, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Min Cao, Jeffrey Markham
  • Publication number: 20120266110
    Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 18, 2012
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Min CAO, Jeffrey MARKHAM