Patents by Inventor Jeffrey Paul Brooks

Jeffrey Paul Brooks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7703085
    Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: April 20, 2010
    Assignee: SRC Computers, Inc.
    Inventors: Daniel Poznanovic, Jeffrey Hammes, Lisa Krause, Jon Steidel, David Barker, Jeffrey Paul Brooks
  • Patent number: 6983456
    Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 3, 2006
    Assignee: SRC Computers, Inc.
    Inventors: Daniel Poznanovic, Jeffrey Hammes, Lisa Krause, Jon Steidel, David Barker, Jeffrey Paul Brooks
  • Publication number: 20040088685
    Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Daniel Poznanovic, Jeffrey Hammes, Lisa Krause, Jon Steidel, David Barker, Jeffrey Paul Brooks