Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.

Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.

Abstract: In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.

Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Abstract: A power semiconductor package, including a leadframe having at least one first terminal, a second terminal and a third terminal. The package also includes a semiconductor power die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a second current carrying electrode and a second metalized region defining a control electrode are disposed, the bottom surface being coupled to the leadframe such that the first terminal is electrically connected to the first current carrying electrode. A clip is also coupled to the first metalized region defining the second current carrying electrode and to the second terminal such that it is electrically coupled to the second current carrying electrode.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A power semiconductor package, including a leadframe having at least one first terminal, a second terminal and a third terminal. The package also includes a semiconductor power die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a second current carrying electrode and a second metalized region defining a control electrode are disposed, the bottom surface being coupled to the leadframe such that the first terminal is electrically connected to the first current carrying electrode. A clip is also coupled to the first metalized region defining the second current carrying electrode and to the second terminal such that it is electrically coupled to the second current carrying electrode.

Abstract: A power semiconductor device including a semiconductor die having electrically active first and second surfaces. A mark is located on the second surface configured to facilitate identification of the device and a metal layer is formed over the second surface of the semiconductor die and over the mark. The metal layer is configured to conduct a current of the device and to allow the mark to be visible for identification purposes.

Abstract: A power semiconductor device including a semiconductor die having electrically active first and second surfaces. A mark is located on the second surface configured to facilitate identification of the device and a metal layer is formed over the second surface of the semiconductor die and over the mark. The metal layer is configured to conduct a current of the device and to allow the mark to be visible for identification purposes.

Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.

Abstract: A masking material (14) is formed on a foundation layer (12) and a substrate (10). A mask (16) is disposed onto the masking material (14) where a trench (26) is desired to be formed. An etch step removes all of the masking material (14) except at regions where the mask (16) was formed leaving a protruding portion (18) with an opening (20) on either side. An epi layer (24), is grown on the foundation layer (12) adjacent to the protruding portion (18) in the opening (20). A wet oxide etch process is used to remove the protruding portion (18) leaving a trench (26) formed in the epi layer (24). To complete the process, a silicon wet etch process is used to round off the corners at an edge (28) of the trench (26).

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.