Patents by Inventor Jeffrey R. Marino
Jeffrey R. Marino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7214608Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.Type: GrantFiled: July 29, 2004Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Peter E. Biolsi, Lawrence A. Clevenger, Habib Hichri, Bernd E. Kastenmeier, Michael W. Lane, Jeffrey R. Marino, Vincent J. McGahay, Theodorus E. Standaert
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Patent number: 7033648Abstract: A method to selectively metallize polyimide with an all-electroless process.Type: GrantFiled: December 30, 1996Date of Patent: April 25, 2006Assignee: International Business Machines CorporationsInventors: Fuad E. Doany, Jeffrey R. Marino, Carlos J. Sambucetti, Ravi F. Saraf
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Patent number: 6831363Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.Type: GrantFiled: December 12, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Sanjit K. Das, Brett H. Engel, Brian W. Herbst, Habib Hichri, Bernd E. Kastenmeier, Kelly Malone, Jeffrey R. Marino, Arthur Martin, Vincent J. McGahay, Ian D. Melville, Chandrasekhar Narayan, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20040152295Abstract: A semiconductor device which includes an improved liner structure formed in a via having extended sidewall portions and a bottom penetrating a metal line. The liner structure includes two liner layers, the first being on the via sidewalls, but not the bottom, and the second being on the first layer and the extended sidewall portions and bottom of the via. A method of making the liner structure, in which the first layer is deposited prior to an etching or cleaning step, which extends the via into the metal line, is also disclosed.Type: ApplicationFiled: February 3, 2003Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Edward C. Cooney, Robert M. Geffken, Jeffrey R. Marino, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20040150103Abstract: A semiconductor device which includes an improved liner structure formed in a via having extended sidewall portions and a bottom penetrating a metal line. The liner structure includes two liner layers, the first being on the via sidewalls, but not the bottom, and the second being on the first layer and the extended sidewall portions and bottom of the via. A method of making the liner structure, in which the first layer is deposited prior to an etching or cleaning step, which extends the via into the metal line, is also disclosed.Type: ApplicationFiled: February 3, 2003Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Edward C. Cooney, Robert M. Geffken, Jeffrey R. Marino, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20040113278Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dalton, Sanjit K. Das, Brett H. Engel, Brian W. Herbst, Habib Hichri, Bernd E. Kastenmeier, Kelly Malone, Jeffrey R. Marino, Arthur Martin, Vincent J. McGahay, Ian D. Melville, Chandrasekhar Narayan, Kevin S. Petrarca, Richard P. Volant
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Patent number: 6661097Abstract: In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.Type: GrantFiled: November 1, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Larry Clevenger, Stanley J. Klepeis, Hsiao-Ling Lu, Jeffrey R. Marino, Andrew Herbert Simon, Yun-Yu Wang, Kwong Hon Wong, Chih-Chao Yang
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Patent number: 6311428Abstract: The invention provides a simple device for providing vertical support of vegetable plants, thereby eliminating the conventional problems routinely associated with home gardening. In particular, the device provides a maintenance free, vertical support frame assembly of adjustable height to which is attached a mesh netting and supporting stakes, forming an extendable garden trellis. Growing plants may be attached to the gardening trellis, thereby allowing maximum upward growth of the plants while also elevating the plants.Type: GrantFiled: January 12, 1999Date of Patent: November 6, 2001Assignee: Vegherb, LLCInventors: Jeffrey R. Marino, Anthony G. Topping
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Patent number: 6202367Abstract: A support bracket and stake are provided which can be used for edging gardens and lawns or for the formation of retaining walls. Used together, the bracket and stake provide a means to support and anchor lengths of lumber to the ground to create a variety of edging systems. In particular, the stakes provide a means to attach the system securely to the ground surface, while the support bracket has a beam receiving portion to support a variety of different types of lumber frequently used in edging. A mounting column on the support bracket provides a means to secure the support bracket to the stakes such that the support bracket may freely rotate 360° perpendicular to the vertical axis of the stake. The stakes may be vertically engaged one upon and inside the other to provide a raised border system of various height.Type: GrantFiled: January 14, 1999Date of Patent: March 20, 2001Assignee: Vegherb, LLCInventors: Jeffrey R. Marino, Anthony G. Topping
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Patent number: 6010918Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.Type: GrantFiled: February 10, 1998Date of Patent: January 4, 2000Assignee: FED CorporationInventors: Jeffrey R. Marino, Joseph K. Ho
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Patent number: 5633047Abstract: Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.Type: GrantFiled: May 24, 1995Date of Patent: May 27, 1997Assignee: International Business Machines CorporationInventors: Michael J. Brady, Curtis E. Farrell, Sung K. Kang, Jeffrey R. Marino, Donald J. Mikalsen, Paul A. Moskowitz, Eugene J. O'Sullivan, Terrence R. O'Toole, Sampath Purushothaman, Sheldon C. Rieley, George F. Walker
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Patent number: D422885Type: GrantFiled: April 22, 1999Date of Patent: April 18, 2000Assignee: Vegherb, LLCInventors: Jeffrey R. Marino, Anthony G. Topping
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Patent number: D423626Type: GrantFiled: June 3, 1999Date of Patent: April 25, 2000Assignee: Vegherb, LLCInventors: Jeffrey R. Marino, Anthony G. Topping
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Patent number: D428798Type: GrantFiled: April 22, 1999Date of Patent: August 1, 2000Assignee: Vegherb, LLCInventors: Jeffrey R. Marino, Anthony G. Topping